base.hh (9294:8fb03b13de02) base.hh (9332:ae2a5329ce96)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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98 int _cpuId;
99
100 /** instruction side request id that must be placed in all requests */
101 MasterID _instMasterId;
102
103 /** data side request id that must be placed in all requests */
104 MasterID _dataMasterId;
105
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 89 unchanged lines hidden (view full) ---

98 int _cpuId;
99
100 /** instruction side request id that must be placed in all requests */
101 MasterID _instMasterId;
102
103 /** data side request id that must be placed in all requests */
104 MasterID _dataMasterId;
105
106 /** An intrenal representation of a task identifier within gem5. This is
107 * used so the CPU can add which taskId (which is an internal representation
108 * of the OS process ID) to each request so components in the memory system
109 * can track which process IDs are ultimately interacting with them
110 */
111 uint32_t _taskId;
112
113 /** The current OS process ID that is executing on this processor. This is
114 * used to generate a taskId */
115 uint32_t _pid;
116
106 /**
107 * Define a base class for the CPU ports (instruction and data)
108 * that is refined in the subclasses. This class handles the
109 * common cases, i.e. the functional accesses and the status
110 * changes and address range queries. The default behaviour for
111 * both atomic and timing access is to panic and the corresponding
112 * subclasses have to override these methods.
113 */

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169 * @param if_name the port name
170 * @param idx ignored index
171 *
172 * @return a reference to the port with the given name
173 */
174 BaseMasterPort &getMasterPort(const std::string &if_name,
175 PortID idx = InvalidPortID);
176
117 /**
118 * Define a base class for the CPU ports (instruction and data)
119 * that is refined in the subclasses. This class handles the
120 * common cases, i.e. the functional accesses and the status
121 * changes and address range queries. The default behaviour for
122 * both atomic and timing access is to panic and the corresponding
123 * subclasses have to override these methods.
124 */

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180 * @param if_name the port name
181 * @param idx ignored index
182 *
183 * @return a reference to the port with the given name
184 */
185 BaseMasterPort &getMasterPort(const std::string &if_name,
186 PortID idx = InvalidPortID);
187
188 /** Get cpu task id */
189 uint32_t taskId() const { return _taskId; }
190 /** Set cpu task id */
191 void taskId(uint32_t id) { _taskId = id; }
192
193 uint32_t getPid() const { return _pid; }
194 void setPid(uint32_t pid) { _pid = pid; }
195
177 inline void workItemBegin() { numWorkItemsStarted++; }
178 inline void workItemEnd() { numWorkItemsCompleted++; }
179 // @todo remove me after debugging with legion done
180 Tick instCount() { return instCnt; }
181
182 TheISA::MicrocodeRom microcodeRom;
183
184 protected:

--- 215 unchanged lines hidden --- 		196 inline void workItemBegin() { numWorkItemsStarted++; }
197 inline void workItemEnd() { numWorkItemsCompleted++; }
198 // @todo remove me after debugging with legion done
199 Tick instCount() { return instCnt; }
200
201 TheISA::MicrocodeRom microcodeRom;
202
203 protected:

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