base.hh (8809:bb10807da889) base.hh (8832:247fee427324)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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99 // @todo remove me after debugging with legion done
100 Tick instCnt;
101 // every cpu has an id, put it in the base cpu
102 // Set at initialization, only time a cpuId might change is during a
103 // takeover (which should be done from within the BaseCPU anyway,
104 // therefore no setCpuId() method is provided
105 int _cpuId;
106
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 90 unchanged lines hidden (view full) ---

99 // @todo remove me after debugging with legion done
100 Tick instCnt;
101 // every cpu has an id, put it in the base cpu
102 // Set at initialization, only time a cpuId might change is during a
103 // takeover (which should be done from within the BaseCPU anyway,
104 // therefore no setCpuId() method is provided
105 int _cpuId;
106
107 /** instruction side request id that must be placed in all requests */
108 MasterID _instMasterId;
109
110 /** data side request id that must be placed in all requests */
111 MasterID _dataMasterId;
112
107 /**
108 * Define a base class for the CPU ports (instruction and data)
109 * that is refined in the subclasses. This class handles the
110 * common cases, i.e. the functional accesses and the status
111 * changes and address range queries. The default behaviour for
112 * both atomic and timing access is to panic and the corresponding
113 * subclasses have to override these methods.
114 */

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139 void recvRangeChange();
140
141 };
142
143 public:
144 /** Reads this CPU's ID. */
145 int cpuId() { return _cpuId; }
146
113 /**
114 * Define a base class for the CPU ports (instruction and data)
115 * that is refined in the subclasses. This class handles the
116 * common cases, i.e. the functional accesses and the status
117 * changes and address range queries. The default behaviour for
118 * both atomic and timing access is to panic and the corresponding
119 * subclasses have to override these methods.
120 */

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145 void recvRangeChange();
146
147 };
148
149 public:
150 /** Reads this CPU's ID. */
151 int cpuId() { return _cpuId; }
152
153 /** Reads this CPU's unique data requestor ID */
154 MasterID dataMasterId() { return _dataMasterId; }
155 /** Reads this CPU's unique instruction requestor ID */
156 MasterID instMasterId() { return _instMasterId; }
157
147// Tick currentTick;
148 inline Tick frequency() const { return SimClock::Frequency / clock; }
149 inline Tick ticks(int numCycles) const { return clock * numCycles; }
150 inline Tick curCycle() const { return curTick() / clock; }
151 inline Tick tickToCycles(Tick val) const { return val / clock; }
152 inline void workItemBegin() { numWorkItemsStarted++; }
153 inline void workItemEnd() { numWorkItemsCompleted++; }
154 // @todo remove me after debugging with legion done

--- 210 unchanged lines hidden --- 		158// Tick currentTick;
159 inline Tick frequency() const { return SimClock::Frequency / clock; }
160 inline Tick ticks(int numCycles) const { return clock * numCycles; }
161 inline Tick curCycle() const { return curTick() / clock; }
162 inline Tick tickToCycles(Tick val) const { return val / clock; }
163 inline void workItemBegin() { numWorkItemsStarted++; }
164 inline void workItemEnd() { numWorkItemsCompleted++; }
165 // @todo remove me after debugging with legion done

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