base.hh (7914:eee5bb0fb8ea) base.hh (8181:f789b9aac5f4)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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234 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
235
236 /**
237 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
238 * This is a constant for the duration of the simulation.
239 */
240 ThreadID numThreads;
241
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 225 unchanged lines hidden (view full) ---

234 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
235
236 /**
237 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
238 * This is a constant for the duration of the simulation.
239 */
240 ThreadID numThreads;
241
242 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
243
244 /**
245 * Vector of per-thread instruction-based event queues. Used for
246 * scheduling events based on number of instructions committed by
247 * a particular thread.
248 */
249 EventQueue **comInstEventQueue;
250
251 /**

--- 75 unchanged lines hidden --- 		242 /**
243 * Vector of per-thread instruction-based event queues. Used for
244 * scheduling events based on number of instructions committed by
245 * a particular thread.
246 */
247 EventQueue **comInstEventQueue;
248
249 /**

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