| base.hh (5100:7a0180040755) | base.hh (5222:bb733a878f85) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 175 unchanged lines hidden (view full) --- 184 185 bool do_statistics_insts; 186 bool do_checkpoint_insts; 187 bool do_quiesce; 188#endif 189 Tick progress_interval; 190 BaseCPU *checker; 191 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 175 unchanged lines hidden (view full) --- 184 185 bool do_statistics_insts; 186 bool do_checkpoint_insts; 187 bool do_quiesce; 188#endif 189 Tick progress_interval; 190 BaseCPU *checker; 191 |
| 192#if THE_ISA == MIPS_ISA 193 /* Note: It looks like it will be better to allow simulator users 194 to specify the values of individual variables instead of requiring 195 users to define the values of entire registers 196 Especially since a lot of these variables can be created from other 197 user parameters (cache descriptions) 198 -jpp 199 */ 200 // MIPS CP0 State - First individual variables 201 // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA) 202 unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt 203 unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt 204 unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set 205 unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options 206 unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS) 207 unsigned CP0_PRId_ProcessorID; // Page 105 208 unsigned CP0_PRId_Revision; // Page 105 209 unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system 210 unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode 211 unsigned CP0_Config_AT; //Page 109 212 unsigned CP0_Config_AR; //Page 109 213 unsigned CP0_Config_MT; //Page 109 214 unsigned CP0_Config_VI; //Page 109 215 unsigned CP0_Config1_M; // Page 110 216 unsigned CP0_Config1_MMU; // Page 110 217 unsigned CP0_Config1_IS; // Page 110 218 unsigned CP0_Config1_IL; // Page 111 219 unsigned CP0_Config1_IA; // Page 111 220 unsigned CP0_Config1_DS; // Page 111 221 unsigned CP0_Config1_DL; // Page 112 222 unsigned CP0_Config1_DA; // Page 112 223 bool CP0_Config1_C2; // Page 112 224 bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32 225 bool CP0_Config1_PC;// Page 112 226 bool CP0_Config1_WR;// Page 113 227 bool CP0_Config1_CA;// Page 113 228 bool CP0_Config1_EP;// Page 113 229 bool CP0_Config1_FP;// Page 113 230 bool CP0_Config2_M; // Page 114 231 unsigned CP0_Config2_TU;// Page 114 232 unsigned CP0_Config2_TS;// Page 114 233 unsigned CP0_Config2_TL;// Page 115 234 unsigned CP0_Config2_TA;// Page 115 235 unsigned CP0_Config2_SU;// Page 115 236 unsigned CP0_Config2_SS;// Page 115 237 unsigned CP0_Config2_SL;// Page 116 238 unsigned CP0_Config2_SA;// Page 116 239 bool CP0_Config3_M; //// Page 117 240 bool CP0_Config3_DSPP;// Page 117 241 bool CP0_Config3_LPA;// Page 117 242 bool CP0_Config3_VEIC;// Page 118 243 bool CP0_Config3_VInt; // Page 118 244 bool CP0_Config3_SP;// Page 118 245 bool CP0_Config3_MT;// Page 119 246 bool CP0_Config3_SM;// Page 119 247 bool CP0_Config3_TL;// Page 119 248 249 bool CP0_WatchHi_M; // Page 124 250 bool CP0_PerfCtr_M; // Page 130 251 bool CP0_PerfCtr_W; // Page 130 252 253 254 // Then, whole registers 255 unsigned CP0_PRId; 256 unsigned CP0_Config; 257 unsigned CP0_Config1; 258 unsigned CP0_Config2; 259 unsigned CP0_Config3; 260 261#endif 262 |
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| 192 Params(); 193 }; 194 195 const Params *params; 196 197 BaseCPU(Params *params); 198 virtual ~BaseCPU(); 199 --- 103 unchanged lines hidden --- | 263 Params(); 264 }; 265 266 const Params *params; 267 268 BaseCPU(Params *params); 269 virtual ~BaseCPU(); 270 --- 103 unchanged lines hidden --- |