base.hh (3495:884bf1f0c0c9) base.hh (3520:4f4a2054fd85)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include <vector>
36
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "sim/eventq.hh"
40#include "mem/mem_object.hh"
41#include "arch/isa_traits.hh"
42
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 26 unchanged lines hidden (view full) ---

35#include <vector>
36
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "sim/eventq.hh"
40#include "mem/mem_object.hh"
41#include "arch/isa_traits.hh"
42
43#if FULL_SYSTEM
44#include "arch/interrupts.hh"
45#endif
46
43class BranchPred;
44class CheckerCPU;
45class ThreadContext;
46class System;
47class Port;
48
49class CPUProgressEvent : public Event
50{

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68 Tick clock;
69
70 public:
71// Tick currentTick;
72 inline Tick frequency() const { return Clock::Frequency / clock; }
73 inline Tick cycles(int numCycles) const { return clock * numCycles; }
74 inline Tick curCycle() const { return curTick / clock; }
75
47class BranchPred;
48class CheckerCPU;
49class ThreadContext;
50class System;
51class Port;
52
53class CPUProgressEvent : public Event
54{

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72 Tick clock;
73
74 public:
75// Tick currentTick;
76 inline Tick frequency() const { return Clock::Frequency / clock; }
77 inline Tick cycles(int numCycles) const { return clock * numCycles; }
78 inline Tick curCycle() const { return curTick / clock; }
79
76 /** The next cycle the CPU should be scheduled, given a cache
77 * access or quiesce event returning on this cycle. This function
78 * may return curTick if the CPU should run on the current cycle.
79 */
80 Tick nextCycle();
81
82 /** The next cycle the CPU should be scheduled, given a cache
83 * access or quiesce event returning on the given Tick. This
84 * function may return curTick if the CPU should run on the
85 * current cycle.
86 * @param begin_tick The tick that the event is completing on.
87 */
88 Tick nextCycle(Tick begin_tick);
89
90#if FULL_SYSTEM
91 protected:
80#if FULL_SYSTEM
81 protected:
92 uint64_t interrupts[TheISA::NumInterruptLevels];
93 uint64_t intstatus;
82// uint64_t interrupts[TheISA::NumInterruptLevels];
83// uint64_t intstatus;
84 TheISA::Interrupts interrupts;
94
95 public:
96 virtual void post_interrupt(int int_num, int index);
97 virtual void clear_interrupt(int int_num, int index);
98 virtual void clear_interrupts();
99 bool checkInterrupts;
100
101 bool check_interrupt(int int_num) const {
85
86 public:
87 virtual void post_interrupt(int int_num, int index);
88 virtual void clear_interrupt(int int_num, int index);
89 virtual void clear_interrupts();
90 bool checkInterrupts;
91
92 bool check_interrupt(int int_num) const {
102 if (int_num > TheISA::NumInterruptLevels)
103 panic("int_num out of bounds\n");
104
105 return interrupts[int_num] != 0;
93 return interrupts.check_interrupt(int_num);
106 }
107
94 }
95
108 bool check_interrupts() const { return intstatus != 0; }
109 uint64_t intr_status() const { return intstatus; }
96 bool check_interrupts() const { return interrupts.check_interrupts(); }
97 //uint64_t intr_status() const { return interrupts.intr_status(); }
110
111 class ProfileEvent : public Event
112 {
113 private:
114 BaseCPU *cpu;
115 int interval;
116
117 public:

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99 class ProfileEvent : public Event
100 {
101 private:
102 BaseCPU *cpu;
103 int interval;
104
105 public:

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