base.hh (10110:580b47334a97) base.hh (10190:fb83d025d1c3)
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 87 unchanged lines hidden (view full) ---

96 // @todo remove me after debugging with legion done
97 Tick instCnt;
98 // every cpu has an id, put it in the base cpu
99 // Set at initialization, only time a cpuId might change is during a
100 // takeover (which should be done from within the BaseCPU anyway,
101 // therefore no setCpuId() method is provided
102 int _cpuId;
103
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 87 unchanged lines hidden (view full) ---

96 // @todo remove me after debugging with legion done
97 Tick instCnt;
98 // every cpu has an id, put it in the base cpu
99 // Set at initialization, only time a cpuId might change is during a
100 // takeover (which should be done from within the BaseCPU anyway,
101 // therefore no setCpuId() method is provided
102 int _cpuId;
103
104 /** Each cpu will have a socket ID that corresponds to its physical location
105 * in the system. This is usually used to bucket cpu cores under single DVFS
106 * domain. This information may also be required by the OS to identify the
107 * cpu core grouping (as in the case of ARM via MPIDR register)
108 */
109 const uint32_t _socketId;
110
104 /** instruction side request id that must be placed in all requests */
105 MasterID _instMasterId;
106
107 /** data side request id that must be placed in all requests */
108 MasterID _dataMasterId;
109
110 /** An intrenal representation of a task identifier within gem5. This is
111 * used so the CPU can add which taskId (which is an internal representation

--- 28 unchanged lines hidden (view full) ---

140 *
141 * @return a reference to the instruction port
142 */
143 virtual MasterPort &getInstPort() = 0;
144
145 /** Reads this CPU's ID. */
146 int cpuId() const { return _cpuId; }
147
111 /** instruction side request id that must be placed in all requests */
112 MasterID _instMasterId;
113
114 /** data side request id that must be placed in all requests */
115 MasterID _dataMasterId;
116
117 /** An intrenal representation of a task identifier within gem5. This is
118 * used so the CPU can add which taskId (which is an internal representation

--- 28 unchanged lines hidden (view full) ---

147 *
148 * @return a reference to the instruction port
149 */
150 virtual MasterPort &getInstPort() = 0;
151
152 /** Reads this CPU's ID. */
153 int cpuId() const { return _cpuId; }
154
155 /** Reads this CPU's Socket ID. */
156 uint32_t socketId() const { return _socketId; }
157
148 /** Reads this CPU's unique data requestor ID */
149 MasterID dataMasterId() { return _dataMasterId; }
150 /** Reads this CPU's unique instruction requestor ID */
151 MasterID instMasterId() { return _instMasterId; }
152
153 /**
154 * Get a master port on this CPU. All CPUs have a data and
155 * instruction port, and this method uses getDataPort and

--- 334 unchanged lines hidden --- 		158 /** Reads this CPU's unique data requestor ID */
159 MasterID dataMasterId() { return _dataMasterId; }
160 /** Reads this CPU's unique instruction requestor ID */
161 MasterID instMasterId() { return _instMasterId; }
162
163 /**
164 * Get a master port on this CPU. All CPUs have a data and
165 * instruction port, and this method uses getDataPort and

--- 334 unchanged lines hidden ---