base.hh (10030:b531e328342d) base.hh (10110:580b47334a97)
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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138 * Purely virtual method that returns a reference to the instruction
139 * port. All subclasses must implement this method.
140 *
141 * @return a reference to the instruction port
142 */
143 virtual MasterPort &getInstPort() = 0;
144
145 /** Reads this CPU's ID. */
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 129 unchanged lines hidden (view full) ---

138 * Purely virtual method that returns a reference to the instruction
139 * port. All subclasses must implement this method.
140 *
141 * @return a reference to the instruction port
142 */
143 virtual MasterPort &getInstPort() = 0;
144
145 /** Reads this CPU's ID. */
146 int cpuId() { return _cpuId; }
146 int cpuId() const { return _cpuId; }
147
148 /** Reads this CPU's unique data requestor ID */
149 MasterID dataMasterId() { return _dataMasterId; }
150 /** Reads this CPU's unique instruction requestor ID */
151 MasterID instMasterId() { return _instMasterId; }
152
153 /**
154 * Get a master port on this CPU. All CPUs have a data and

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148 /** Reads this CPU's unique data requestor ID */
149 MasterID dataMasterId() { return _dataMasterId; }
150 /** Reads this CPU's unique instruction requestor ID */
151 MasterID instMasterId() { return _instMasterId; }
152
153 /**
154 * Get a master port on this CPU. All CPUs have a data and

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