1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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3 * Copyright (c) 2011 Regents of the University of California |
4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Steve Reinhardt 30 * Nathan Binkert
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31 * Rick Strong |
32 */ 33 34#ifndef __CPU_BASE_HH__ 35#define __CPU_BASE_HH__ 36 37#include <vector> 38 39#include "arch/isa_traits.hh" 40#include "arch/microcode_rom.hh" 41#include "base/statistics.hh" 42#include "config/full_system.hh" 43#include "config/the_isa.hh" 44#include "sim/eventq.hh" 45#include "sim/insttracer.hh" 46#include "mem/mem_object.hh" 47 48#if FULL_SYSTEM 49#include "arch/interrupts.hh" 50#endif 51 52class BaseCPUParams; 53class BranchPred; 54class CheckerCPU; 55class ThreadContext; 56class System; 57class Port; 58 59namespace TheISA 60{ 61 class Predecoder; 62} 63 64class CPUProgressEvent : public Event 65{ 66 protected: 67 Tick _interval; 68 Counter lastNumInst; 69 BaseCPU *cpu; 70 bool _repeatEvent; 71 72 public: 73 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 74 75 void process(); 76 77 void interval(Tick ival) { _interval = ival; } 78 Tick interval() { return _interval; } 79 80 void repeatEvent(bool repeat) { _repeatEvent = repeat; } 81 82 virtual const char *description() const; 83}; 84 85class BaseCPU : public MemObject 86{ 87 protected: 88 // CPU's clock period in terms of the number of ticks of curTime. 89 Tick clock; 90 // @todo remove me after debugging with legion done 91 Tick instCnt; 92 // every cpu has an id, put it in the base cpu 93 // Set at initialization, only time a cpuId might change is during a 94 // takeover (which should be done from within the BaseCPU anyway, 95 // therefore no setCpuId() method is provided 96 int _cpuId; 97 98 public: 99 /** Reads this CPU's ID. */ 100 int cpuId() { return _cpuId; } 101 102// Tick currentTick; 103 inline Tick frequency() const { return SimClock::Frequency / clock; } 104 inline Tick ticks(int numCycles) const { return clock * numCycles; } 105 inline Tick curCycle() const { return curTick() / clock; } 106 inline Tick tickToCycles(Tick val) const { return val / clock; } 107 // @todo remove me after debugging with legion done 108 Tick instCount() { return instCnt; } 109 110 /** The next cycle the CPU should be scheduled, given a cache 111 * access or quiesce event returning on this cycle. This function 112 * may return curTick() if the CPU should run on the current cycle. 113 */ 114 Tick nextCycle(); 115 116 /** The next cycle the CPU should be scheduled, given a cache 117 * access or quiesce event returning on the given Tick. This 118 * function may return curTick() if the CPU should run on the 119 * current cycle. 120 * @param begin_tick The tick that the event is completing on. 121 */ 122 Tick nextCycle(Tick begin_tick); 123 124 TheISA::MicrocodeRom microcodeRom; 125 126#if FULL_SYSTEM 127 protected: 128 TheISA::Interrupts *interrupts; 129 130 public: 131 TheISA::Interrupts * 132 getInterruptController() 133 { 134 return interrupts; 135 } 136 137 virtual void wakeup() = 0; 138 139 void 140 postInterrupt(int int_num, int index) 141 { 142 interrupts->post(int_num, index); 143 wakeup(); 144 } 145 146 void 147 clearInterrupt(int int_num, int index) 148 { 149 interrupts->clear(int_num, index); 150 } 151 152 void 153 clearInterrupts() 154 { 155 interrupts->clearAll(); 156 } 157 158 bool 159 checkInterrupts(ThreadContext *tc) const 160 { 161 return interrupts->checkInterrupts(tc); 162 } 163 164 class ProfileEvent : public Event 165 { 166 private: 167 BaseCPU *cpu; 168 Tick interval; 169 170 public: 171 ProfileEvent(BaseCPU *cpu, Tick interval); 172 void process(); 173 }; 174 ProfileEvent *profileEvent; 175#endif 176 177 protected: 178 std::vector<ThreadContext *> threadContexts; 179 std::vector<TheISA::Predecoder *> predecoders; 180 181 Trace::InstTracer * tracer; 182 183 public: 184 185 // Mask to align PCs to MachInst sized boundaries 186 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 187 188 /// Provide access to the tracer pointer 189 Trace::InstTracer * getTracer() { return tracer; } 190 191 /// Notify the CPU that the indicated context is now active. The 192 /// delay parameter indicates the number of ticks to wait before 193 /// executing (typically 0 or 1). 194 virtual void activateContext(int thread_num, int delay) {} 195 196 /// Notify the CPU that the indicated context is now suspended. 197 virtual void suspendContext(int thread_num) {} 198 199 /// Notify the CPU that the indicated context is now deallocated. 200 virtual void deallocateContext(int thread_num) {} 201 202 /// Notify the CPU that the indicated context is now halted. 203 virtual void haltContext(int thread_num) {} 204 205 /// Given a Thread Context pointer return the thread num 206 int findContext(ThreadContext *tc); 207 208 /// Given a thread num get tho thread context for it 209 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 210 211 public: 212 typedef BaseCPUParams Params; 213 const Params *params() const 214 { return reinterpret_cast<const Params *>(_params); } 215 BaseCPU(Params *params); 216 virtual ~BaseCPU(); 217 218 virtual void init(); 219 virtual void startup(); 220 virtual void regStats(); 221 222 virtual void activateWhenReady(ThreadID tid) {}; 223 224 void registerThreadContexts(); 225 226 /// Prepare for another CPU to take over execution. When it is 227 /// is ready (drained pipe) it signals the sampler. 228 virtual void switchOut(); 229 230 /// Take over execution from the given CPU. Used for warm-up and 231 /// sampling. 232 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 233 234 /** 235 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 236 * This is a constant for the duration of the simulation. 237 */ 238 ThreadID numThreads; 239 240 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 241 242 /** 243 * Vector of per-thread instruction-based event queues. Used for 244 * scheduling events based on number of instructions committed by 245 * a particular thread. 246 */ 247 EventQueue **comInstEventQueue; 248 249 /** 250 * Vector of per-thread load-based event queues. Used for 251 * scheduling events based on number of loads committed by 252 *a particular thread. 253 */ 254 EventQueue **comLoadEventQueue; 255 256 System *system; 257 258 Tick phase; 259 260#if FULL_SYSTEM 261 /** 262 * Serialize this object to the given output stream. 263 * @param os The stream to serialize to. 264 */ 265 virtual void serialize(std::ostream &os); 266 267 /** 268 * Reconstruct the state of this object from a checkpoint. 269 * @param cp The checkpoint use. 270 * @param section The section name of this object 271 */ 272 virtual void unserialize(Checkpoint *cp, const std::string §ion); 273 274#endif 275 276 /** 277 * Return pointer to CPU's branch predictor (NULL if none). 278 * @return Branch predictor pointer. 279 */ 280 virtual BranchPred *getBranchPred() { return NULL; }; 281 282 virtual Counter totalInstructions() const = 0; 283 284 // Function tracing 285 private: 286 bool functionTracingEnabled; 287 std::ostream *functionTraceStream; 288 Addr currentFunctionStart; 289 Addr currentFunctionEnd; 290 Tick functionEntryTick; 291 void enableFunctionTrace(); 292 void traceFunctionsInternal(Addr pc); 293 294 protected: 295 void traceFunctions(Addr pc) 296 { 297 if (functionTracingEnabled) 298 traceFunctionsInternal(pc); 299 } 300 301 private: 302 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 303 304 public: 305 static int numSimulatedCPUs() { return cpuList.size(); } 306 static Counter numSimulatedInstructions() 307 { 308 Counter total = 0; 309 310 int size = cpuList.size(); 311 for (int i = 0; i < size; ++i) 312 total += cpuList[i]->totalInstructions(); 313 314 return total; 315 } 316 317 public: 318 // Number of CPU cycles simulated 319 Stats::Scalar numCycles; 320}; 321 322#endif // __CPU_BASE_HH__
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