1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "arch/isa_traits.hh" 38#include "base/statistics.hh" 39#include "config/full_system.hh" 40#include "sim/eventq.hh" 41#include "sim/insttracer.hh" 42#include "mem/mem_object.hh" 43 44#if FULL_SYSTEM 45#include "arch/interrupts.hh" 46#endif 47 48class BaseCPUParams; 49class BranchPred; 50class CheckerCPU; 51class ThreadContext; 52class System; 53class Port; 54 55namespace TheISA 56{ 57 class Predecoder; 58} 59 60class CPUProgressEvent : public Event 61{ 62 protected: 63 Tick interval; 64 Counter lastNumInst; 65 BaseCPU *cpu; 66 67 public: 68 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 69 70 void process(); 71 72 virtual const char *description() const; 73}; 74 75class BaseCPU : public MemObject 76{ 77 protected: 78 // CPU's clock period in terms of the number of ticks of curTime. 79 Tick clock; 80 // @todo remove me after debugging with legion done 81 Tick instCnt; 82 83 public: 84// Tick currentTick; 85 inline Tick frequency() const { return Clock::Frequency / clock; } 86 inline Tick ticks(int numCycles) const { return clock * numCycles; } 87 inline Tick curCycle() const { return curTick / clock; } 88 inline Tick tickToCycles(Tick val) const { return val / clock; } 89 // @todo remove me after debugging with legion done 90 Tick instCount() { return instCnt; } 91 92 /** The next cycle the CPU should be scheduled, given a cache 93 * access or quiesce event returning on this cycle. This function 94 * may return curTick if the CPU should run on the current cycle. 95 */ 96 Tick nextCycle(); 97 98 /** The next cycle the CPU should be scheduled, given a cache 99 * access or quiesce event returning on the given Tick. This 100 * function may return curTick if the CPU should run on the 101 * current cycle. 102 * @param begin_tick The tick that the event is completing on. 103 */ 104 Tick nextCycle(Tick begin_tick); 105 106#if FULL_SYSTEM 107 protected: 108// uint64_t interrupts[TheISA::NumInterruptLevels]; 109// uint64_t intstatus; 110 TheISA::Interrupts interrupts; 111 112 public: 113 virtual void post_interrupt(int int_num, int index); 114 virtual void clear_interrupt(int int_num, int index); 115 virtual void clear_interrupts(); 116 virtual uint64_t get_interrupts(int int_num); 117 118 bool check_interrupts(ThreadContext * tc) const 119 { return interrupts.check_interrupts(tc); } 120 121 class ProfileEvent : public Event 122 { 123 private: 124 BaseCPU *cpu;
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