1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 264 unchanged lines hidden (view full) --- 273 virtual void init(); 274 virtual void startup(); 275 virtual void regStats(); 276 277 virtual void activateWhenReady(ThreadID tid) {}; 278 279 void registerThreadContexts(); 280 |
281 /** 282 * Prepare for another CPU to take over execution. 283 * 284 * When this method exits, all internal state should have been 285 * flushed. After the method returns, the simulator calls 286 * takeOverFrom() on the new CPU with this CPU as its parameter. 287 */ |
288 virtual void switchOut(); 289 |
290 /** 291 * Load the state of a CPU from the previous CPU object, invoked 292 * on all new CPUs that are about to be switched in. 293 * 294 * A CPU model implementing this method is expected to initialize 295 * its state from the old CPU and connect its memory (unless they 296 * are already connected) to the memories connected to the old 297 * CPU. 298 * 299 * @param cpu CPU to initialize read state from. 300 */ 301 virtual void takeOverFrom(BaseCPU *cpu); |
302 303 /** 304 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 305 * This is a constant for the duration of the simulation. 306 */ 307 ThreadID numThreads; 308 309 /** --- 89 unchanged lines hidden --- |