1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "arch/isa_traits.hh" |
38#include "arch/microcode_rom.hh" |
39#include "base/statistics.hh" 40#include "config/full_system.hh" 41#include "sim/eventq.hh" 42#include "sim/insttracer.hh" 43#include "mem/mem_object.hh" 44 45#if FULL_SYSTEM 46#include "arch/interrupts.hh" --- 52 unchanged lines hidden (view full) --- 99 /** The next cycle the CPU should be scheduled, given a cache 100 * access or quiesce event returning on the given Tick. This 101 * function may return curTick if the CPU should run on the 102 * current cycle. 103 * @param begin_tick The tick that the event is completing on. 104 */ 105 Tick nextCycle(Tick begin_tick); 106 |
107 TheISA::MicrocodeRom microcodeRom; 108 |
109#if FULL_SYSTEM 110 protected: 111// uint64_t interrupts[TheISA::NumInterruptLevels]; 112// uint64_t intstatus; 113 TheISA::Interrupts * interrupts; 114 115 public: 116 TheISA::Interrupts * --- 168 unchanged lines hidden --- |