1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 |
37#include "arch/isa_traits.hh" |
38#include "base/statistics.hh" 39#include "config/full_system.hh" 40#include "sim/eventq.hh" 41#include "mem/mem_object.hh" |
42 43#if FULL_SYSTEM 44#include "arch/interrupts.hh" 45#endif 46 47class BranchPred; 48class CheckerCPU; 49class ThreadContext; 50class System; 51class Port; 52 |
53namespace TheISA 54{ 55 class Predecoder; 56} 57 |
58class CPUProgressEvent : public Event 59{ 60 protected: 61 Tick interval; 62 Counter lastNumInst; 63 BaseCPU *cpu; 64 65 public: --- 59 unchanged lines hidden (view full) --- 125 ProfileEvent(BaseCPU *cpu, int interval); 126 void process(); 127 }; 128 ProfileEvent *profileEvent; 129#endif 130 131 protected: 132 std::vector<ThreadContext *> threadContexts; |
133 std::vector<TheISA::Predecoder *> predecoders; |
134 135 public: 136 137 /// Notify the CPU that the indicated context is now active. The 138 /// delay parameter indicates the number of ticks to wait before 139 /// executing (typically 0 or 1). 140 virtual void activateContext(int thread_num, int delay) {} 141 --- 152 unchanged lines hidden --- |