1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 63 unchanged lines hidden (view full) --- 72 Tick clock; 73 74 public: 75// Tick currentTick; 76 inline Tick frequency() const { return Clock::Frequency / clock; } 77 inline Tick cycles(int numCycles) const { return clock * numCycles; } 78 inline Tick curCycle() const { return curTick / clock; } 79 |
80 /** The next cycle the CPU should be scheduled, given a cache 81 * access or quiesce event returning on this cycle. This function 82 * may return curTick if the CPU should run on the current cycle. 83 */ 84 Tick nextCycle(); 85 86 /** The next cycle the CPU should be scheduled, given a cache 87 * access or quiesce event returning on the given Tick. This 88 * function may return curTick if the CPU should run on the 89 * current cycle. 90 * @param begin_tick The tick that the event is completing on. 91 */ 92 Tick nextCycle(Tick begin_tick); 93 |
94#if FULL_SYSTEM 95 protected: 96// uint64_t interrupts[TheISA::NumInterruptLevels]; 97// uint64_t intstatus; 98 TheISA::Interrupts interrupts; 99 100 public: 101 virtual void post_interrupt(int int_num, int index); --- 169 unchanged lines hidden --- |