1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 59 unchanged lines hidden (view full) --- 68 Tick clock; 69 70 public: 71// Tick currentTick; 72 inline Tick frequency() const { return Clock::Frequency / clock; } 73 inline Tick cycles(int numCycles) const { return clock * numCycles; } 74 inline Tick curCycle() const { return curTick / clock; } 75 |
76 /** The next cycle the CPU should be scheduled, given a cache 77 * access or quiesce event returning on this cycle. This function 78 * may return curTick if the CPU should run on the current cycle. 79 */ 80 Tick nextCycle(); 81 82 /** The next cycle the CPU should be scheduled, given a cache 83 * access or quiesce event returning on the given Tick. This 84 * function may return curTick if the CPU should run on the 85 * current cycle. 86 * @param begin_tick The tick that the event is completing on. 87 */ 88 Tick nextCycle(Tick begin_tick); 89 |
90#if FULL_SYSTEM 91 protected: 92 uint64_t interrupts[TheISA::NumInterruptLevels]; 93 uint64_t intstatus; 94 95 public: 96 virtual void post_interrupt(int int_num, int index); 97 virtual void clear_interrupt(int int_num, int index); --- 175 unchanged lines hidden --- |