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< * Copyright (c) 2011-2012 ARM Limited
---
> * Copyright (c) 2011-2013 ARM Limited
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< /**
< * Define a base class for the CPU ports (instruction and data)
< * that is refined in the subclasses. This class handles the
< * common cases, i.e. the functional accesses and the status
< * changes and address range queries. The default behaviour for
< * both atomic and timing access is to panic and the corresponding
< * subclasses have to override these methods.
< */
< class CpuPort : public MasterPort
< {
< public:
<
< /**
< * Create a CPU port with a name and a structural owner.
< *
< * @param _name port name including the owner
< * @param _name structural owner of this port
< */
< CpuPort(const std::string& _name, MemObject* _owner) :
< MasterPort(_name, _owner)
< { }
<
< protected:
<
< virtual bool recvTimingResp(PacketPtr pkt);
<
< virtual void recvRetry();
<
< virtual void recvFunctionalSnoop(PacketPtr pkt);
<
< };
<
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< virtual CpuPort &getDataPort() = 0;
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> virtual MasterPort &getDataPort() = 0;
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< virtual CpuPort &getInstPort() = 0;
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> virtual MasterPort &getInstPort() = 0;