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< * Get a master port on this MemObject. This method is virtual to allow
< * the subclasses of the BaseCPU to override it. All CPUs have a
< * data and instruction port, but the Atomic CPU (in its current
< * form) adds a port directly connected to the memory and has to
< * override getMasterPort.
---
> * Get a master port on this CPU. All CPUs have a data and
> * instruction port, and this method uses getDataPort and
> * getInstPort of the subclasses to resolve the two ports.
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< * This method uses getDataPort and getInstPort to resolve the two
< * ports.
< *
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< virtual MasterPort &getMasterPort(const std::string &if_name,
< int idx = -1);
---
> MasterPort &getMasterPort(const std::string &if_name, int idx = -1);