1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#ifndef __CPU_BASE_HH__
47#define __CPU_BASE_HH__
48
49#include <vector>
50
51#include "arch/interrupts.hh"
52#include "arch/isa_traits.hh"
53#include "arch/microcode_rom.hh"
54#include "base/statistics.hh"
55#include "config/the_isa.hh"
56#include "mem/mem_object.hh"
57#include "sim/eventq.hh"
58#include "sim/full_system.hh"
59#include "sim/insttracer.hh"
60
61struct BaseCPUParams;
62class BranchPred;
63class CheckerCPU;
64class ThreadContext;
65class System;
66
67class CPUProgressEvent : public Event
68{
69 protected:
70 Tick _interval;
71 Counter lastNumInst;
72 BaseCPU *cpu;
73 bool _repeatEvent;
74
75 public:
76 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
77
78 void process();
79
80 void interval(Tick ival) { _interval = ival; }
81 Tick interval() { return _interval; }
82
83 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
84
85 virtual const char *description() const;
86};
87
88class BaseCPU : public MemObject
89{
90 protected:
91
92 // @todo remove me after debugging with legion done
93 Tick instCnt;
94 // every cpu has an id, put it in the base cpu
95 // Set at initialization, only time a cpuId might change is during a
96 // takeover (which should be done from within the BaseCPU anyway,
97 // therefore no setCpuId() method is provided
98 int _cpuId;
99
100 /** instruction side request id that must be placed in all requests */
101 MasterID _instMasterId;
102
103 /** data side request id that must be placed in all requests */
104 MasterID _dataMasterId;
105
106 /** An intrenal representation of a task identifier within gem5. This is
107 * used so the CPU can add which taskId (which is an internal representation
108 * of the OS process ID) to each request so components in the memory system
109 * can track which process IDs are ultimately interacting with them
110 */
111 uint32_t _taskId;
112
113 /** The current OS process ID that is executing on this processor. This is
114 * used to generate a taskId */
115 uint32_t _pid;
116
117 /** Is the CPU switched out or active? */
118 bool _switchedOut;
119
120 /**
121 * Define a base class for the CPU ports (instruction and data)
122 * that is refined in the subclasses. This class handles the
123 * common cases, i.e. the functional accesses and the status
124 * changes and address range queries. The default behaviour for
125 * both atomic and timing access is to panic and the corresponding
126 * subclasses have to override these methods.
127 */
128 class CpuPort : public MasterPort
129 {
130 public:
131
132 /**
133 * Create a CPU port with a name and a structural owner.
134 *
135 * @param _name port name including the owner
136 * @param _name structural owner of this port
137 */
138 CpuPort(const std::string& _name, MemObject* _owner) :
139 MasterPort(_name, _owner)
140 { }
141
142 protected:
143
144 virtual bool recvTimingResp(PacketPtr pkt);
145
146 virtual void recvRetry();
147
148 virtual void recvFunctionalSnoop(PacketPtr pkt);
149
150 };
151
152 public:
153
154 /**
155 * Purely virtual method that returns a reference to the data
156 * port. All subclasses must implement this method.
157 *
158 * @return a reference to the data port
159 */
160 virtual CpuPort &getDataPort() = 0;
161
162 /**
163 * Purely virtual method that returns a reference to the instruction
164 * port. All subclasses must implement this method.
165 *
166 * @return a reference to the instruction port
167 */
168 virtual CpuPort &getInstPort() = 0;
169
170 /** Reads this CPU's ID. */
171 int cpuId() { return _cpuId; }
172
173 /** Reads this CPU's unique data requestor ID */
174 MasterID dataMasterId() { return _dataMasterId; }
175 /** Reads this CPU's unique instruction requestor ID */
176 MasterID instMasterId() { return _instMasterId; }
177
178 /**
179 * Get a master port on this CPU. All CPUs have a data and
180 * instruction port, and this method uses getDataPort and
181 * getInstPort of the subclasses to resolve the two ports.
182 *
183 * @param if_name the port name
184 * @param idx ignored index
185 *
186 * @return a reference to the port with the given name
187 */
188 BaseMasterPort &getMasterPort(const std::string &if_name,
189 PortID idx = InvalidPortID);
190
191 /** Get cpu task id */
192 uint32_t taskId() const { return _taskId; }
193 /** Set cpu task id */
194 void taskId(uint32_t id) { _taskId = id; }
195
196 uint32_t getPid() const { return _pid; }
197 void setPid(uint32_t pid) { _pid = pid; }
198
199 inline void workItemBegin() { numWorkItemsStarted++; }
200 inline void workItemEnd() { numWorkItemsCompleted++; }
201 // @todo remove me after debugging with legion done
202 Tick instCount() { return instCnt; }
203
204 TheISA::MicrocodeRom microcodeRom;
205
206 protected:
207 TheISA::Interrupts *interrupts;
208
209 public:
210 TheISA::Interrupts *
211 getInterruptController()
212 {
213 return interrupts;
214 }
215
216 virtual void wakeup() = 0;
217
218 void
219 postInterrupt(int int_num, int index)
220 {
221 interrupts->post(int_num, index);
222 if (FullSystem)
223 wakeup();
224 }
225
226 void
227 clearInterrupt(int int_num, int index)
228 {
229 interrupts->clear(int_num, index);
230 }
231
232 void
233 clearInterrupts()
234 {
235 interrupts->clearAll();
236 }
237
238 bool
239 checkInterrupts(ThreadContext *tc) const
240 {
241 return FullSystem && interrupts->checkInterrupts(tc);
242 }
243
244 class ProfileEvent : public Event
245 {
246 private:
247 BaseCPU *cpu;
248 Tick interval;
249
250 public:
251 ProfileEvent(BaseCPU *cpu, Tick interval);
252 void process();
253 };
254 ProfileEvent *profileEvent;
255
256 protected:
257 std::vector<ThreadContext *> threadContexts;
258
259 Trace::InstTracer * tracer;
260
261 public:
262
263 // Mask to align PCs to MachInst sized boundaries
264 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
265
266 /// Provide access to the tracer pointer
267 Trace::InstTracer * getTracer() { return tracer; }
268
269 /// Notify the CPU that the indicated context is now active. The
270 /// delay parameter indicates the number of ticks to wait before
271 /// executing (typically 0 or 1).
272 virtual void activateContext(ThreadID thread_num, Cycles delay) {}
273
274 /// Notify the CPU that the indicated context is now suspended.
275 virtual void suspendContext(ThreadID thread_num) {}
276
277 /// Notify the CPU that the indicated context is now deallocated.
278 virtual void deallocateContext(ThreadID thread_num) {}
279
280 /// Notify the CPU that the indicated context is now halted.
281 virtual void haltContext(ThreadID thread_num) {}
282
283 /// Given a Thread Context pointer return the thread num
284 int findContext(ThreadContext *tc);
285
286 /// Given a thread num get tho thread context for it
287 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
288
289 public:
290 typedef BaseCPUParams Params;
291 const Params *params() const
292 { return reinterpret_cast<const Params *>(_params); }
293 BaseCPU(Params *params, bool is_checker = false);
294 virtual ~BaseCPU();
295
296 virtual void init();
297 virtual void startup();
298 virtual void regStats();
299
300 virtual void activateWhenReady(ThreadID tid) {};
301
302 void registerThreadContexts();
303
304 /**
305 * Prepare for another CPU to take over execution.
306 *
307 * When this method exits, all internal state should have been
308 * flushed. After the method returns, the simulator calls
309 * takeOverFrom() on the new CPU with this CPU as its parameter.
310 */
311 virtual void switchOut();
312
313 /**
314 * Load the state of a CPU from the previous CPU object, invoked
315 * on all new CPUs that are about to be switched in.
316 *
317 * A CPU model implementing this method is expected to initialize
318 * its state from the old CPU and connect its memory (unless they
319 * are already connected) to the memories connected to the old
320 * CPU.
321 *
322 * @param cpu CPU to initialize read state from.
323 */
324 virtual void takeOverFrom(BaseCPU *cpu);
325
326 /**
327 * Flush all TLBs in the CPU.
328 *
329 * This method is mainly used to flush stale translations when
330 * switching CPUs. It is also exported to the Python world to
331 * allow it to request a TLB flush after draining the CPU to make
332 * it easier to compare traces when debugging
333 * handover/checkpointing.
334 */
335 void flushTLBs();
336
337 /**
338 * Determine if the CPU is switched out.
339 *
340 * @return True if the CPU is switched out, false otherwise.
341 */
342 bool switchedOut() const { return _switchedOut; }
343
344 /**
345 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
346 * This is a constant for the duration of the simulation.
347 */
348 ThreadID numThreads;
349
350 /**
351 * Vector of per-thread instruction-based event queues. Used for
352 * scheduling events based on number of instructions committed by
353 * a particular thread.
354 */
355 EventQueue **comInstEventQueue;
356
357 /**
358 * Vector of per-thread load-based event queues. Used for
359 * scheduling events based on number of loads committed by
360 *a particular thread.
361 */
362 EventQueue **comLoadEventQueue;
363
364 System *system;
365
366 /**
367 * Serialize this object to the given output stream.
| 1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#ifndef __CPU_BASE_HH__
47#define __CPU_BASE_HH__
48
49#include <vector>
50
51#include "arch/interrupts.hh"
52#include "arch/isa_traits.hh"
53#include "arch/microcode_rom.hh"
54#include "base/statistics.hh"
55#include "config/the_isa.hh"
56#include "mem/mem_object.hh"
57#include "sim/eventq.hh"
58#include "sim/full_system.hh"
59#include "sim/insttracer.hh"
60
61struct BaseCPUParams;
62class BranchPred;
63class CheckerCPU;
64class ThreadContext;
65class System;
66
67class CPUProgressEvent : public Event
68{
69 protected:
70 Tick _interval;
71 Counter lastNumInst;
72 BaseCPU *cpu;
73 bool _repeatEvent;
74
75 public:
76 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
77
78 void process();
79
80 void interval(Tick ival) { _interval = ival; }
81 Tick interval() { return _interval; }
82
83 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
84
85 virtual const char *description() const;
86};
87
88class BaseCPU : public MemObject
89{
90 protected:
91
92 // @todo remove me after debugging with legion done
93 Tick instCnt;
94 // every cpu has an id, put it in the base cpu
95 // Set at initialization, only time a cpuId might change is during a
96 // takeover (which should be done from within the BaseCPU anyway,
97 // therefore no setCpuId() method is provided
98 int _cpuId;
99
100 /** instruction side request id that must be placed in all requests */
101 MasterID _instMasterId;
102
103 /** data side request id that must be placed in all requests */
104 MasterID _dataMasterId;
105
106 /** An intrenal representation of a task identifier within gem5. This is
107 * used so the CPU can add which taskId (which is an internal representation
108 * of the OS process ID) to each request so components in the memory system
109 * can track which process IDs are ultimately interacting with them
110 */
111 uint32_t _taskId;
112
113 /** The current OS process ID that is executing on this processor. This is
114 * used to generate a taskId */
115 uint32_t _pid;
116
117 /** Is the CPU switched out or active? */
118 bool _switchedOut;
119
120 /**
121 * Define a base class for the CPU ports (instruction and data)
122 * that is refined in the subclasses. This class handles the
123 * common cases, i.e. the functional accesses and the status
124 * changes and address range queries. The default behaviour for
125 * both atomic and timing access is to panic and the corresponding
126 * subclasses have to override these methods.
127 */
128 class CpuPort : public MasterPort
129 {
130 public:
131
132 /**
133 * Create a CPU port with a name and a structural owner.
134 *
135 * @param _name port name including the owner
136 * @param _name structural owner of this port
137 */
138 CpuPort(const std::string& _name, MemObject* _owner) :
139 MasterPort(_name, _owner)
140 { }
141
142 protected:
143
144 virtual bool recvTimingResp(PacketPtr pkt);
145
146 virtual void recvRetry();
147
148 virtual void recvFunctionalSnoop(PacketPtr pkt);
149
150 };
151
152 public:
153
154 /**
155 * Purely virtual method that returns a reference to the data
156 * port. All subclasses must implement this method.
157 *
158 * @return a reference to the data port
159 */
160 virtual CpuPort &getDataPort() = 0;
161
162 /**
163 * Purely virtual method that returns a reference to the instruction
164 * port. All subclasses must implement this method.
165 *
166 * @return a reference to the instruction port
167 */
168 virtual CpuPort &getInstPort() = 0;
169
170 /** Reads this CPU's ID. */
171 int cpuId() { return _cpuId; }
172
173 /** Reads this CPU's unique data requestor ID */
174 MasterID dataMasterId() { return _dataMasterId; }
175 /** Reads this CPU's unique instruction requestor ID */
176 MasterID instMasterId() { return _instMasterId; }
177
178 /**
179 * Get a master port on this CPU. All CPUs have a data and
180 * instruction port, and this method uses getDataPort and
181 * getInstPort of the subclasses to resolve the two ports.
182 *
183 * @param if_name the port name
184 * @param idx ignored index
185 *
186 * @return a reference to the port with the given name
187 */
188 BaseMasterPort &getMasterPort(const std::string &if_name,
189 PortID idx = InvalidPortID);
190
191 /** Get cpu task id */
192 uint32_t taskId() const { return _taskId; }
193 /** Set cpu task id */
194 void taskId(uint32_t id) { _taskId = id; }
195
196 uint32_t getPid() const { return _pid; }
197 void setPid(uint32_t pid) { _pid = pid; }
198
199 inline void workItemBegin() { numWorkItemsStarted++; }
200 inline void workItemEnd() { numWorkItemsCompleted++; }
201 // @todo remove me after debugging with legion done
202 Tick instCount() { return instCnt; }
203
204 TheISA::MicrocodeRom microcodeRom;
205
206 protected:
207 TheISA::Interrupts *interrupts;
208
209 public:
210 TheISA::Interrupts *
211 getInterruptController()
212 {
213 return interrupts;
214 }
215
216 virtual void wakeup() = 0;
217
218 void
219 postInterrupt(int int_num, int index)
220 {
221 interrupts->post(int_num, index);
222 if (FullSystem)
223 wakeup();
224 }
225
226 void
227 clearInterrupt(int int_num, int index)
228 {
229 interrupts->clear(int_num, index);
230 }
231
232 void
233 clearInterrupts()
234 {
235 interrupts->clearAll();
236 }
237
238 bool
239 checkInterrupts(ThreadContext *tc) const
240 {
241 return FullSystem && interrupts->checkInterrupts(tc);
242 }
243
244 class ProfileEvent : public Event
245 {
246 private:
247 BaseCPU *cpu;
248 Tick interval;
249
250 public:
251 ProfileEvent(BaseCPU *cpu, Tick interval);
252 void process();
253 };
254 ProfileEvent *profileEvent;
255
256 protected:
257 std::vector<ThreadContext *> threadContexts;
258
259 Trace::InstTracer * tracer;
260
261 public:
262
263 // Mask to align PCs to MachInst sized boundaries
264 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
265
266 /// Provide access to the tracer pointer
267 Trace::InstTracer * getTracer() { return tracer; }
268
269 /// Notify the CPU that the indicated context is now active. The
270 /// delay parameter indicates the number of ticks to wait before
271 /// executing (typically 0 or 1).
272 virtual void activateContext(ThreadID thread_num, Cycles delay) {}
273
274 /// Notify the CPU that the indicated context is now suspended.
275 virtual void suspendContext(ThreadID thread_num) {}
276
277 /// Notify the CPU that the indicated context is now deallocated.
278 virtual void deallocateContext(ThreadID thread_num) {}
279
280 /// Notify the CPU that the indicated context is now halted.
281 virtual void haltContext(ThreadID thread_num) {}
282
283 /// Given a Thread Context pointer return the thread num
284 int findContext(ThreadContext *tc);
285
286 /// Given a thread num get tho thread context for it
287 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
288
289 public:
290 typedef BaseCPUParams Params;
291 const Params *params() const
292 { return reinterpret_cast<const Params *>(_params); }
293 BaseCPU(Params *params, bool is_checker = false);
294 virtual ~BaseCPU();
295
296 virtual void init();
297 virtual void startup();
298 virtual void regStats();
299
300 virtual void activateWhenReady(ThreadID tid) {};
301
302 void registerThreadContexts();
303
304 /**
305 * Prepare for another CPU to take over execution.
306 *
307 * When this method exits, all internal state should have been
308 * flushed. After the method returns, the simulator calls
309 * takeOverFrom() on the new CPU with this CPU as its parameter.
310 */
311 virtual void switchOut();
312
313 /**
314 * Load the state of a CPU from the previous CPU object, invoked
315 * on all new CPUs that are about to be switched in.
316 *
317 * A CPU model implementing this method is expected to initialize
318 * its state from the old CPU and connect its memory (unless they
319 * are already connected) to the memories connected to the old
320 * CPU.
321 *
322 * @param cpu CPU to initialize read state from.
323 */
324 virtual void takeOverFrom(BaseCPU *cpu);
325
326 /**
327 * Flush all TLBs in the CPU.
328 *
329 * This method is mainly used to flush stale translations when
330 * switching CPUs. It is also exported to the Python world to
331 * allow it to request a TLB flush after draining the CPU to make
332 * it easier to compare traces when debugging
333 * handover/checkpointing.
334 */
335 void flushTLBs();
336
337 /**
338 * Determine if the CPU is switched out.
339 *
340 * @return True if the CPU is switched out, false otherwise.
341 */
342 bool switchedOut() const { return _switchedOut; }
343
344 /**
345 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
346 * This is a constant for the duration of the simulation.
347 */
348 ThreadID numThreads;
349
350 /**
351 * Vector of per-thread instruction-based event queues. Used for
352 * scheduling events based on number of instructions committed by
353 * a particular thread.
354 */
355 EventQueue **comInstEventQueue;
356
357 /**
358 * Vector of per-thread load-based event queues. Used for
359 * scheduling events based on number of loads committed by
360 *a particular thread.
361 */
362 EventQueue **comLoadEventQueue;
363
364 System *system;
365
366 /**
367 * Serialize this object to the given output stream.
|