base.hh (8975:7f36d4436074) base.hh (9023:e9201a7bce59)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#ifndef __CPU_BASE_HH__
47#define __CPU_BASE_HH__
48
49#include <vector>
50
51#include "arch/interrupts.hh"
52#include "arch/isa_traits.hh"
53#include "arch/microcode_rom.hh"
54#include "base/statistics.hh"
55#include "config/the_isa.hh"
56#include "mem/mem_object.hh"
57#include "sim/eventq.hh"
58#include "sim/full_system.hh"
59#include "sim/insttracer.hh"
60
61struct BaseCPUParams;
62class BranchPred;
63class CheckerCPU;
64class ThreadContext;
65class System;
66
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#ifndef __CPU_BASE_HH__
47#define __CPU_BASE_HH__
48
49#include <vector>
50
51#include "arch/interrupts.hh"
52#include "arch/isa_traits.hh"
53#include "arch/microcode_rom.hh"
54#include "base/statistics.hh"
55#include "config/the_isa.hh"
56#include "mem/mem_object.hh"
57#include "sim/eventq.hh"
58#include "sim/full_system.hh"
59#include "sim/insttracer.hh"
60
61struct BaseCPUParams;
62class BranchPred;
63class CheckerCPU;
64class ThreadContext;
65class System;
66
67namespace TheISA
68{
69 class Predecoder;
70}
71
72class CPUProgressEvent : public Event
73{
74 protected:
75 Tick _interval;
76 Counter lastNumInst;
77 BaseCPU *cpu;
78 bool _repeatEvent;
79
80 public:
81 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
82
83 void process();
84
85 void interval(Tick ival) { _interval = ival; }
86 Tick interval() { return _interval; }
87
88 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
89
90 virtual const char *description() const;
91};
92
93class BaseCPU : public MemObject
94{
95 protected:
96 // CPU's clock period in terms of the number of ticks of curTime.
97 Tick clock;
98 // @todo remove me after debugging with legion done
99 Tick instCnt;
100 // every cpu has an id, put it in the base cpu
101 // Set at initialization, only time a cpuId might change is during a
102 // takeover (which should be done from within the BaseCPU anyway,
103 // therefore no setCpuId() method is provided
104 int _cpuId;
105
106 /** instruction side request id that must be placed in all requests */
107 MasterID _instMasterId;
108
109 /** data side request id that must be placed in all requests */
110 MasterID _dataMasterId;
111
112 /**
113 * Define a base class for the CPU ports (instruction and data)
114 * that is refined in the subclasses. This class handles the
115 * common cases, i.e. the functional accesses and the status
116 * changes and address range queries. The default behaviour for
117 * both atomic and timing access is to panic and the corresponding
118 * subclasses have to override these methods.
119 */
120 class CpuPort : public MasterPort
121 {
122 public:
123
124 /**
125 * Create a CPU port with a name and a structural owner.
126 *
127 * @param _name port name including the owner
128 * @param _name structural owner of this port
129 */
130 CpuPort(const std::string& _name, MemObject* _owner) :
131 MasterPort(_name, _owner)
132 { }
133
134 protected:
135
136 virtual bool recvTimingResp(PacketPtr pkt);
137
138 virtual void recvRetry();
139
140 virtual void recvFunctionalSnoop(PacketPtr pkt);
141
142 };
143
144 public:
145
146 /**
147 * Purely virtual method that returns a reference to the data
148 * port. All subclasses must implement this method.
149 *
150 * @return a reference to the data port
151 */
152 virtual CpuPort &getDataPort() = 0;
153
154 /**
155 * Purely virtual method that returns a reference to the instruction
156 * port. All subclasses must implement this method.
157 *
158 * @return a reference to the instruction port
159 */
160 virtual CpuPort &getInstPort() = 0;
161
162 /** Reads this CPU's ID. */
163 int cpuId() { return _cpuId; }
164
165 /** Reads this CPU's unique data requestor ID */
166 MasterID dataMasterId() { return _dataMasterId; }
167 /** Reads this CPU's unique instruction requestor ID */
168 MasterID instMasterId() { return _instMasterId; }
169
170 /**
171 * Get a master port on this CPU. All CPUs have a data and
172 * instruction port, and this method uses getDataPort and
173 * getInstPort of the subclasses to resolve the two ports.
174 *
175 * @param if_name the port name
176 * @param idx ignored index
177 *
178 * @return a reference to the port with the given name
179 */
180 MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
181
182// Tick currentTick;
183 inline Tick frequency() const { return SimClock::Frequency / clock; }
184 inline Tick ticks(int numCycles) const { return clock * numCycles; }
185 inline Tick curCycle() const { return curTick() / clock; }
186 inline Tick tickToCycles(Tick val) const { return val / clock; }
187 inline void workItemBegin() { numWorkItemsStarted++; }
188 inline void workItemEnd() { numWorkItemsCompleted++; }
189 // @todo remove me after debugging with legion done
190 Tick instCount() { return instCnt; }
191
192 /** The next cycle the CPU should be scheduled, given a cache
193 * access or quiesce event returning on this cycle. This function
194 * may return curTick() if the CPU should run on the current cycle.
195 */
196 Tick nextCycle();
197
198 /** The next cycle the CPU should be scheduled, given a cache
199 * access or quiesce event returning on the given Tick. This
200 * function may return curTick() if the CPU should run on the
201 * current cycle.
202 * @param begin_tick The tick that the event is completing on.
203 */
204 Tick nextCycle(Tick begin_tick);
205
206 TheISA::MicrocodeRom microcodeRom;
207
208 protected:
209 TheISA::Interrupts *interrupts;
210
211 public:
212 TheISA::Interrupts *
213 getInterruptController()
214 {
215 return interrupts;
216 }
217
218 virtual void wakeup() = 0;
219
220 void
221 postInterrupt(int int_num, int index)
222 {
223 interrupts->post(int_num, index);
224 if (FullSystem)
225 wakeup();
226 }
227
228 void
229 clearInterrupt(int int_num, int index)
230 {
231 interrupts->clear(int_num, index);
232 }
233
234 void
235 clearInterrupts()
236 {
237 interrupts->clearAll();
238 }
239
240 bool
241 checkInterrupts(ThreadContext *tc) const
242 {
243 return FullSystem && interrupts->checkInterrupts(tc);
244 }
245
246 class ProfileEvent : public Event
247 {
248 private:
249 BaseCPU *cpu;
250 Tick interval;
251
252 public:
253 ProfileEvent(BaseCPU *cpu, Tick interval);
254 void process();
255 };
256 ProfileEvent *profileEvent;
257
258 protected:
259 std::vector<ThreadContext *> threadContexts;
67class CPUProgressEvent : public Event
68{
69 protected:
70 Tick _interval;
71 Counter lastNumInst;
72 BaseCPU *cpu;
73 bool _repeatEvent;
74
75 public:
76 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
77
78 void process();
79
80 void interval(Tick ival) { _interval = ival; }
81 Tick interval() { return _interval; }
82
83 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
84
85 virtual const char *description() const;
86};
87
88class BaseCPU : public MemObject
89{
90 protected:
91 // CPU's clock period in terms of the number of ticks of curTime.
92 Tick clock;
93 // @todo remove me after debugging with legion done
94 Tick instCnt;
95 // every cpu has an id, put it in the base cpu
96 // Set at initialization, only time a cpuId might change is during a
97 // takeover (which should be done from within the BaseCPU anyway,
98 // therefore no setCpuId() method is provided
99 int _cpuId;
100
101 /** instruction side request id that must be placed in all requests */
102 MasterID _instMasterId;
103
104 /** data side request id that must be placed in all requests */
105 MasterID _dataMasterId;
106
107 /**
108 * Define a base class for the CPU ports (instruction and data)
109 * that is refined in the subclasses. This class handles the
110 * common cases, i.e. the functional accesses and the status
111 * changes and address range queries. The default behaviour for
112 * both atomic and timing access is to panic and the corresponding
113 * subclasses have to override these methods.
114 */
115 class CpuPort : public MasterPort
116 {
117 public:
118
119 /**
120 * Create a CPU port with a name and a structural owner.
121 *
122 * @param _name port name including the owner
123 * @param _name structural owner of this port
124 */
125 CpuPort(const std::string& _name, MemObject* _owner) :
126 MasterPort(_name, _owner)
127 { }
128
129 protected:
130
131 virtual bool recvTimingResp(PacketPtr pkt);
132
133 virtual void recvRetry();
134
135 virtual void recvFunctionalSnoop(PacketPtr pkt);
136
137 };
138
139 public:
140
141 /**
142 * Purely virtual method that returns a reference to the data
143 * port. All subclasses must implement this method.
144 *
145 * @return a reference to the data port
146 */
147 virtual CpuPort &getDataPort() = 0;
148
149 /**
150 * Purely virtual method that returns a reference to the instruction
151 * port. All subclasses must implement this method.
152 *
153 * @return a reference to the instruction port
154 */
155 virtual CpuPort &getInstPort() = 0;
156
157 /** Reads this CPU's ID. */
158 int cpuId() { return _cpuId; }
159
160 /** Reads this CPU's unique data requestor ID */
161 MasterID dataMasterId() { return _dataMasterId; }
162 /** Reads this CPU's unique instruction requestor ID */
163 MasterID instMasterId() { return _instMasterId; }
164
165 /**
166 * Get a master port on this CPU. All CPUs have a data and
167 * instruction port, and this method uses getDataPort and
168 * getInstPort of the subclasses to resolve the two ports.
169 *
170 * @param if_name the port name
171 * @param idx ignored index
172 *
173 * @return a reference to the port with the given name
174 */
175 MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
176
177// Tick currentTick;
178 inline Tick frequency() const { return SimClock::Frequency / clock; }
179 inline Tick ticks(int numCycles) const { return clock * numCycles; }
180 inline Tick curCycle() const { return curTick() / clock; }
181 inline Tick tickToCycles(Tick val) const { return val / clock; }
182 inline void workItemBegin() { numWorkItemsStarted++; }
183 inline void workItemEnd() { numWorkItemsCompleted++; }
184 // @todo remove me after debugging with legion done
185 Tick instCount() { return instCnt; }
186
187 /** The next cycle the CPU should be scheduled, given a cache
188 * access or quiesce event returning on this cycle. This function
189 * may return curTick() if the CPU should run on the current cycle.
190 */
191 Tick nextCycle();
192
193 /** The next cycle the CPU should be scheduled, given a cache
194 * access or quiesce event returning on the given Tick. This
195 * function may return curTick() if the CPU should run on the
196 * current cycle.
197 * @param begin_tick The tick that the event is completing on.
198 */
199 Tick nextCycle(Tick begin_tick);
200
201 TheISA::MicrocodeRom microcodeRom;
202
203 protected:
204 TheISA::Interrupts *interrupts;
205
206 public:
207 TheISA::Interrupts *
208 getInterruptController()
209 {
210 return interrupts;
211 }
212
213 virtual void wakeup() = 0;
214
215 void
216 postInterrupt(int int_num, int index)
217 {
218 interrupts->post(int_num, index);
219 if (FullSystem)
220 wakeup();
221 }
222
223 void
224 clearInterrupt(int int_num, int index)
225 {
226 interrupts->clear(int_num, index);
227 }
228
229 void
230 clearInterrupts()
231 {
232 interrupts->clearAll();
233 }
234
235 bool
236 checkInterrupts(ThreadContext *tc) const
237 {
238 return FullSystem && interrupts->checkInterrupts(tc);
239 }
240
241 class ProfileEvent : public Event
242 {
243 private:
244 BaseCPU *cpu;
245 Tick interval;
246
247 public:
248 ProfileEvent(BaseCPU *cpu, Tick interval);
249 void process();
250 };
251 ProfileEvent *profileEvent;
252
253 protected:
254 std::vector<ThreadContext *> threadContexts;
260 std::vector<TheISA::Predecoder *> predecoders;
261
262 Trace::InstTracer * tracer;
263
264 public:
265
266 // Mask to align PCs to MachInst sized boundaries
267 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
268
269 /// Provide access to the tracer pointer
270 Trace::InstTracer * getTracer() { return tracer; }
271
272 /// Notify the CPU that the indicated context is now active. The
273 /// delay parameter indicates the number of ticks to wait before
274 /// executing (typically 0 or 1).
275 virtual void activateContext(ThreadID thread_num, int delay) {}
276
277 /// Notify the CPU that the indicated context is now suspended.
278 virtual void suspendContext(ThreadID thread_num) {}
279
280 /// Notify the CPU that the indicated context is now deallocated.
281 virtual void deallocateContext(ThreadID thread_num) {}
282
283 /// Notify the CPU that the indicated context is now halted.
284 virtual void haltContext(ThreadID thread_num) {}
285
286 /// Given a Thread Context pointer return the thread num
287 int findContext(ThreadContext *tc);
288
289 /// Given a thread num get tho thread context for it
290 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
291
292 public:
293 typedef BaseCPUParams Params;
294 const Params *params() const
295 { return reinterpret_cast<const Params *>(_params); }
296 BaseCPU(Params *params, bool is_checker = false);
297 virtual ~BaseCPU();
298
299 virtual void init();
300 virtual void startup();
301 virtual void regStats();
302
303 virtual void activateWhenReady(ThreadID tid) {};
304
305 void registerThreadContexts();
306
307 /// Prepare for another CPU to take over execution. When it is
308 /// is ready (drained pipe) it signals the sampler.
309 virtual void switchOut();
310
311 /// Take over execution from the given CPU. Used for warm-up and
312 /// sampling.
313 virtual void takeOverFrom(BaseCPU *);
314
315 /**
316 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
317 * This is a constant for the duration of the simulation.
318 */
319 ThreadID numThreads;
320
321 /**
322 * Vector of per-thread instruction-based event queues. Used for
323 * scheduling events based on number of instructions committed by
324 * a particular thread.
325 */
326 EventQueue **comInstEventQueue;
327
328 /**
329 * Vector of per-thread load-based event queues. Used for
330 * scheduling events based on number of loads committed by
331 *a particular thread.
332 */
333 EventQueue **comLoadEventQueue;
334
335 System *system;
336
337 Tick phase;
338
339 /**
340 * Serialize this object to the given output stream.
341 * @param os The stream to serialize to.
342 */
343 virtual void serialize(std::ostream &os);
344
345 /**
346 * Reconstruct the state of this object from a checkpoint.
347 * @param cp The checkpoint use.
348 * @param section The section name of this object
349 */
350 virtual void unserialize(Checkpoint *cp, const std::string &section);
351
352 /**
353 * Return pointer to CPU's branch predictor (NULL if none).
354 * @return Branch predictor pointer.
355 */
356 virtual BranchPred *getBranchPred() { return NULL; };
357
358 virtual Counter totalInsts() const = 0;
359
360 virtual Counter totalOps() const = 0;
361
362 // Function tracing
363 private:
364 bool functionTracingEnabled;
365 std::ostream *functionTraceStream;
366 Addr currentFunctionStart;
367 Addr currentFunctionEnd;
368 Tick functionEntryTick;
369 void enableFunctionTrace();
370 void traceFunctionsInternal(Addr pc);
371
372 private:
373 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
374
375 public:
376 void traceFunctions(Addr pc)
377 {
378 if (functionTracingEnabled)
379 traceFunctionsInternal(pc);
380 }
381
382 static int numSimulatedCPUs() { return cpuList.size(); }
383 static Counter numSimulatedInsts()
384 {
385 Counter total = 0;
386
387 int size = cpuList.size();
388 for (int i = 0; i < size; ++i)
389 total += cpuList[i]->totalInsts();
390
391 return total;
392 }
393
394 static Counter numSimulatedOps()
395 {
396 Counter total = 0;
397
398 int size = cpuList.size();
399 for (int i = 0; i < size; ++i)
400 total += cpuList[i]->totalOps();
401
402 return total;
403 }
404
405 public:
406 // Number of CPU cycles simulated
407 Stats::Scalar numCycles;
408 Stats::Scalar numWorkItemsStarted;
409 Stats::Scalar numWorkItemsCompleted;
410};
411
412#endif // __CPU_BASE_HH__
255
256 Trace::InstTracer * tracer;
257
258 public:
259
260 // Mask to align PCs to MachInst sized boundaries
261 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
262
263 /// Provide access to the tracer pointer
264 Trace::InstTracer * getTracer() { return tracer; }
265
266 /// Notify the CPU that the indicated context is now active. The
267 /// delay parameter indicates the number of ticks to wait before
268 /// executing (typically 0 or 1).
269 virtual void activateContext(ThreadID thread_num, int delay) {}
270
271 /// Notify the CPU that the indicated context is now suspended.
272 virtual void suspendContext(ThreadID thread_num) {}
273
274 /// Notify the CPU that the indicated context is now deallocated.
275 virtual void deallocateContext(ThreadID thread_num) {}
276
277 /// Notify the CPU that the indicated context is now halted.
278 virtual void haltContext(ThreadID thread_num) {}
279
280 /// Given a Thread Context pointer return the thread num
281 int findContext(ThreadContext *tc);
282
283 /// Given a thread num get tho thread context for it
284 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
285
286 public:
287 typedef BaseCPUParams Params;
288 const Params *params() const
289 { return reinterpret_cast<const Params *>(_params); }
290 BaseCPU(Params *params, bool is_checker = false);
291 virtual ~BaseCPU();
292
293 virtual void init();
294 virtual void startup();
295 virtual void regStats();
296
297 virtual void activateWhenReady(ThreadID tid) {};
298
299 void registerThreadContexts();
300
301 /// Prepare for another CPU to take over execution. When it is
302 /// is ready (drained pipe) it signals the sampler.
303 virtual void switchOut();
304
305 /// Take over execution from the given CPU. Used for warm-up and
306 /// sampling.
307 virtual void takeOverFrom(BaseCPU *);
308
309 /**
310 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
311 * This is a constant for the duration of the simulation.
312 */
313 ThreadID numThreads;
314
315 /**
316 * Vector of per-thread instruction-based event queues. Used for
317 * scheduling events based on number of instructions committed by
318 * a particular thread.
319 */
320 EventQueue **comInstEventQueue;
321
322 /**
323 * Vector of per-thread load-based event queues. Used for
324 * scheduling events based on number of loads committed by
325 *a particular thread.
326 */
327 EventQueue **comLoadEventQueue;
328
329 System *system;
330
331 Tick phase;
332
333 /**
334 * Serialize this object to the given output stream.
335 * @param os The stream to serialize to.
336 */
337 virtual void serialize(std::ostream &os);
338
339 /**
340 * Reconstruct the state of this object from a checkpoint.
341 * @param cp The checkpoint use.
342 * @param section The section name of this object
343 */
344 virtual void unserialize(Checkpoint *cp, const std::string &section);
345
346 /**
347 * Return pointer to CPU's branch predictor (NULL if none).
348 * @return Branch predictor pointer.
349 */
350 virtual BranchPred *getBranchPred() { return NULL; };
351
352 virtual Counter totalInsts() const = 0;
353
354 virtual Counter totalOps() const = 0;
355
356 // Function tracing
357 private:
358 bool functionTracingEnabled;
359 std::ostream *functionTraceStream;
360 Addr currentFunctionStart;
361 Addr currentFunctionEnd;
362 Tick functionEntryTick;
363 void enableFunctionTrace();
364 void traceFunctionsInternal(Addr pc);
365
366 private:
367 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
368
369 public:
370 void traceFunctions(Addr pc)
371 {
372 if (functionTracingEnabled)
373 traceFunctionsInternal(pc);
374 }
375
376 static int numSimulatedCPUs() { return cpuList.size(); }
377 static Counter numSimulatedInsts()
378 {
379 Counter total = 0;
380
381 int size = cpuList.size();
382 for (int i = 0; i < size; ++i)
383 total += cpuList[i]->totalInsts();
384
385 return total;
386 }
387
388 static Counter numSimulatedOps()
389 {
390 Counter total = 0;
391
392 int size = cpuList.size();
393 for (int i = 0; i < size; ++i)
394 total += cpuList[i]->totalOps();
395
396 return total;
397 }
398
399 public:
400 // Number of CPU cycles simulated
401 Stats::Scalar numCycles;
402 Stats::Scalar numWorkItemsStarted;
403 Stats::Scalar numWorkItemsCompleted;
404};
405
406#endif // __CPU_BASE_HH__