1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#ifndef __CPU_BASE_HH__
47#define __CPU_BASE_HH__
48
49#include <vector>
50
51#include "arch/interrupts.hh"
52#include "arch/isa_traits.hh"
53#include "arch/microcode_rom.hh"
54#include "base/statistics.hh"
55#include "config/the_isa.hh"
56#include "mem/mem_object.hh"
57#include "sim/eventq.hh"
58#include "sim/full_system.hh"
59#include "sim/insttracer.hh"
60
61class BaseCPUParams;
62class BranchPred;
63class CheckerCPU;
64class ThreadContext;
65class System;
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#ifndef __CPU_BASE_HH__
47#define __CPU_BASE_HH__
48
49#include <vector>
50
51#include "arch/interrupts.hh"
52#include "arch/isa_traits.hh"
53#include "arch/microcode_rom.hh"
54#include "base/statistics.hh"
55#include "config/the_isa.hh"
56#include "mem/mem_object.hh"
57#include "sim/eventq.hh"
58#include "sim/full_system.hh"
59#include "sim/insttracer.hh"
60
61class BaseCPUParams;
62class BranchPred;
63class CheckerCPU;
64class ThreadContext;
65class System;
|
66class Port;
| |
67
68namespace TheISA
69{
70 class Predecoder;
71}
72
73class CPUProgressEvent : public Event
74{
75 protected:
76 Tick _interval;
77 Counter lastNumInst;
78 BaseCPU *cpu;
79 bool _repeatEvent;
80
81 public:
82 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
83
84 void process();
85
86 void interval(Tick ival) { _interval = ival; }
87 Tick interval() { return _interval; }
88
89 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
90
91 virtual const char *description() const;
92};
93
94class BaseCPU : public MemObject
95{
96 protected:
97 // CPU's clock period in terms of the number of ticks of curTime.
98 Tick clock;
99 // @todo remove me after debugging with legion done
100 Tick instCnt;
101 // every cpu has an id, put it in the base cpu
102 // Set at initialization, only time a cpuId might change is during a
103 // takeover (which should be done from within the BaseCPU anyway,
104 // therefore no setCpuId() method is provided
105 int _cpuId;
106
107 /** instruction side request id that must be placed in all requests */
108 MasterID _instMasterId;
109
110 /** data side request id that must be placed in all requests */
111 MasterID _dataMasterId;
112
113 /**
114 * Define a base class for the CPU ports (instruction and data)
115 * that is refined in the subclasses. This class handles the
116 * common cases, i.e. the functional accesses and the status
117 * changes and address range queries. The default behaviour for
118 * both atomic and timing access is to panic and the corresponding
119 * subclasses have to override these methods.
120 */
121 class CpuPort : public Port
122 {
123 public:
124
125 /**
126 * Create a CPU port with a name and a structural owner.
127 *
128 * @param _name port name including the owner
129 * @param _name structural owner of this port
130 */
131 CpuPort(const std::string& _name, MemObject* _owner) :
132 Port(_name, _owner)
133 { }
134
135 protected:
136
137 virtual bool recvTiming(PacketPtr pkt);
138
139 virtual Tick recvAtomic(PacketPtr pkt);
140
141 virtual void recvRetry();
142
143 void recvFunctional(PacketPtr pkt);
144
145 void recvRangeChange();
146
147 };
148
149 public:
| 66
67namespace TheISA
68{
69 class Predecoder;
70}
71
72class CPUProgressEvent : public Event
73{
74 protected:
75 Tick _interval;
76 Counter lastNumInst;
77 BaseCPU *cpu;
78 bool _repeatEvent;
79
80 public:
81 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
82
83 void process();
84
85 void interval(Tick ival) { _interval = ival; }
86 Tick interval() { return _interval; }
87
88 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
89
90 virtual const char *description() const;
91};
92
93class BaseCPU : public MemObject
94{
95 protected:
96 // CPU's clock period in terms of the number of ticks of curTime.
97 Tick clock;
98 // @todo remove me after debugging with legion done
99 Tick instCnt;
100 // every cpu has an id, put it in the base cpu
101 // Set at initialization, only time a cpuId might change is during a
102 // takeover (which should be done from within the BaseCPU anyway,
103 // therefore no setCpuId() method is provided
104 int _cpuId;
105
106 /** instruction side request id that must be placed in all requests */
107 MasterID _instMasterId;
108
109 /** data side request id that must be placed in all requests */
110 MasterID _dataMasterId;
111
112 /**
113 * Define a base class for the CPU ports (instruction and data)
114 * that is refined in the subclasses. This class handles the
115 * common cases, i.e. the functional accesses and the status
116 * changes and address range queries. The default behaviour for
117 * both atomic and timing access is to panic and the corresponding
118 * subclasses have to override these methods.
119 */
120 class CpuPort : public Port
121 {
122 public:
123
124 /**
125 * Create a CPU port with a name and a structural owner.
126 *
127 * @param _name port name including the owner
128 * @param _name structural owner of this port
129 */
130 CpuPort(const std::string& _name, MemObject* _owner) :
131 Port(_name, _owner)
132 { }
133
134 protected:
135
136 virtual bool recvTiming(PacketPtr pkt);
137
138 virtual Tick recvAtomic(PacketPtr pkt);
139
140 virtual void recvRetry();
141
142 void recvFunctional(PacketPtr pkt);
143
144 void recvRangeChange();
145
146 };
147
148 public:
|
| 149
150 /**
151 * Purely virtual method that returns a reference to the data
152 * port. All subclasses must implement this method.
153 *
154 * @return a reference to the data port
155 */
156 virtual CpuPort &getDataPort() = 0;
157
158 /**
159 * Purely virtual method that returns a reference to the instruction
160 * port. All subclasses must implement this method.
161 *
162 * @return a reference to the instruction port
163 */
164 virtual CpuPort &getInstPort() = 0;
165
|
150 /** Reads this CPU's ID. */
151 int cpuId() { return _cpuId; }
152
153 /** Reads this CPU's unique data requestor ID */
154 MasterID dataMasterId() { return _dataMasterId; }
155 /** Reads this CPU's unique instruction requestor ID */
156 MasterID instMasterId() { return _instMasterId; }
157
| 166 /** Reads this CPU's ID. */
167 int cpuId() { return _cpuId; }
168
169 /** Reads this CPU's unique data requestor ID */
170 MasterID dataMasterId() { return _dataMasterId; }
171 /** Reads this CPU's unique instruction requestor ID */
172 MasterID instMasterId() { return _instMasterId; }
173
|
| 174 /**
175 * Get a port on this MemObject. This method is virtual to allow
176 * the subclasses of the BaseCPU to override it. All CPUs have a
177 * data and instruction port, but the Atomic CPU (in its current
178 * form) adds a port directly connected to the memory and has to
179 * override getPort.
180 *
181 * This method uses getDataPort and getInstPort to resolve the two
182 * ports.
183 *
184 * @param if_name the port name
185 * @param idx ignored index
186 *
187 * @return a pointer to the port with the given name
188 */
189 virtual Port *getPort(const std::string &if_name, int idx = -1);
190
|
158// Tick currentTick;
159 inline Tick frequency() const { return SimClock::Frequency / clock; }
160 inline Tick ticks(int numCycles) const { return clock * numCycles; }
161 inline Tick curCycle() const { return curTick() / clock; }
162 inline Tick tickToCycles(Tick val) const { return val / clock; }
163 inline void workItemBegin() { numWorkItemsStarted++; }
164 inline void workItemEnd() { numWorkItemsCompleted++; }
165 // @todo remove me after debugging with legion done
166 Tick instCount() { return instCnt; }
167
168 /** The next cycle the CPU should be scheduled, given a cache
169 * access or quiesce event returning on this cycle. This function
170 * may return curTick() if the CPU should run on the current cycle.
171 */
172 Tick nextCycle();
173
174 /** The next cycle the CPU should be scheduled, given a cache
175 * access or quiesce event returning on the given Tick. This
176 * function may return curTick() if the CPU should run on the
177 * current cycle.
178 * @param begin_tick The tick that the event is completing on.
179 */
180 Tick nextCycle(Tick begin_tick);
181
182 TheISA::MicrocodeRom microcodeRom;
183
184 protected:
185 TheISA::Interrupts *interrupts;
186
187 public:
188 TheISA::Interrupts *
189 getInterruptController()
190 {
191 return interrupts;
192 }
193
194 virtual void wakeup() = 0;
195
196 void
197 postInterrupt(int int_num, int index)
198 {
199 interrupts->post(int_num, index);
200 if (FullSystem)
201 wakeup();
202 }
203
204 void
205 clearInterrupt(int int_num, int index)
206 {
207 interrupts->clear(int_num, index);
208 }
209
210 void
211 clearInterrupts()
212 {
213 interrupts->clearAll();
214 }
215
216 bool
217 checkInterrupts(ThreadContext *tc) const
218 {
219 return FullSystem && interrupts->checkInterrupts(tc);
220 }
221
222 class ProfileEvent : public Event
223 {
224 private:
225 BaseCPU *cpu;
226 Tick interval;
227
228 public:
229 ProfileEvent(BaseCPU *cpu, Tick interval);
230 void process();
231 };
232 ProfileEvent *profileEvent;
233
234 protected:
235 std::vector<ThreadContext *> threadContexts;
236 std::vector<TheISA::Predecoder *> predecoders;
237
238 Trace::InstTracer * tracer;
239
240 public:
241
242 // Mask to align PCs to MachInst sized boundaries
243 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
244
245 /// Provide access to the tracer pointer
246 Trace::InstTracer * getTracer() { return tracer; }
247
248 /// Notify the CPU that the indicated context is now active. The
249 /// delay parameter indicates the number of ticks to wait before
250 /// executing (typically 0 or 1).
251 virtual void activateContext(ThreadID thread_num, int delay) {}
252
253 /// Notify the CPU that the indicated context is now suspended.
254 virtual void suspendContext(ThreadID thread_num) {}
255
256 /// Notify the CPU that the indicated context is now deallocated.
257 virtual void deallocateContext(ThreadID thread_num) {}
258
259 /// Notify the CPU that the indicated context is now halted.
260 virtual void haltContext(ThreadID thread_num) {}
261
262 /// Given a Thread Context pointer return the thread num
263 int findContext(ThreadContext *tc);
264
265 /// Given a thread num get tho thread context for it
266 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
267
268 public:
269 typedef BaseCPUParams Params;
270 const Params *params() const
271 { return reinterpret_cast<const Params *>(_params); }
272 BaseCPU(Params *params);
273 virtual ~BaseCPU();
274
275 virtual void init();
276 virtual void startup();
277 virtual void regStats();
278
279 virtual void activateWhenReady(ThreadID tid) {};
280
281 void registerThreadContexts();
282
283 /// Prepare for another CPU to take over execution. When it is
284 /// is ready (drained pipe) it signals the sampler.
285 virtual void switchOut();
286
287 /// Take over execution from the given CPU. Used for warm-up and
288 /// sampling.
289 virtual void takeOverFrom(BaseCPU *);
290
291 /**
292 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
293 * This is a constant for the duration of the simulation.
294 */
295 ThreadID numThreads;
296
297 /**
298 * Vector of per-thread instruction-based event queues. Used for
299 * scheduling events based on number of instructions committed by
300 * a particular thread.
301 */
302 EventQueue **comInstEventQueue;
303
304 /**
305 * Vector of per-thread load-based event queues. Used for
306 * scheduling events based on number of loads committed by
307 *a particular thread.
308 */
309 EventQueue **comLoadEventQueue;
310
311 System *system;
312
313 Tick phase;
314
315 /**
316 * Serialize this object to the given output stream.
317 * @param os The stream to serialize to.
318 */
319 virtual void serialize(std::ostream &os);
320
321 /**
322 * Reconstruct the state of this object from a checkpoint.
323 * @param cp The checkpoint use.
324 * @param section The section name of this object
325 */
326 virtual void unserialize(Checkpoint *cp, const std::string §ion);
327
328 /**
329 * Return pointer to CPU's branch predictor (NULL if none).
330 * @return Branch predictor pointer.
331 */
332 virtual BranchPred *getBranchPred() { return NULL; };
333
334 virtual Counter totalInsts() const = 0;
335
336 virtual Counter totalOps() const = 0;
337
338 // Function tracing
339 private:
340 bool functionTracingEnabled;
341 std::ostream *functionTraceStream;
342 Addr currentFunctionStart;
343 Addr currentFunctionEnd;
344 Tick functionEntryTick;
345 void enableFunctionTrace();
346 void traceFunctionsInternal(Addr pc);
347
348 private:
349 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
350
351 public:
352 void traceFunctions(Addr pc)
353 {
354 if (functionTracingEnabled)
355 traceFunctionsInternal(pc);
356 }
357
358 static int numSimulatedCPUs() { return cpuList.size(); }
359 static Counter numSimulatedInsts()
360 {
361 Counter total = 0;
362
363 int size = cpuList.size();
364 for (int i = 0; i < size; ++i)
365 total += cpuList[i]->totalInsts();
366
367 return total;
368 }
369
370 static Counter numSimulatedOps()
371 {
372 Counter total = 0;
373
374 int size = cpuList.size();
375 for (int i = 0; i < size; ++i)
376 total += cpuList[i]->totalOps();
377
378 return total;
379 }
380
381 public:
382 // Number of CPU cycles simulated
383 Stats::Scalar numCycles;
384 Stats::Scalar numWorkItemsStarted;
385 Stats::Scalar numWorkItemsCompleted;
386};
387
388#endif // __CPU_BASE_HH__
| 191// Tick currentTick;
192 inline Tick frequency() const { return SimClock::Frequency / clock; }
193 inline Tick ticks(int numCycles) const { return clock * numCycles; }
194 inline Tick curCycle() const { return curTick() / clock; }
195 inline Tick tickToCycles(Tick val) const { return val / clock; }
196 inline void workItemBegin() { numWorkItemsStarted++; }
197 inline void workItemEnd() { numWorkItemsCompleted++; }
198 // @todo remove me after debugging with legion done
199 Tick instCount() { return instCnt; }
200
201 /** The next cycle the CPU should be scheduled, given a cache
202 * access or quiesce event returning on this cycle. This function
203 * may return curTick() if the CPU should run on the current cycle.
204 */
205 Tick nextCycle();
206
207 /** The next cycle the CPU should be scheduled, given a cache
208 * access or quiesce event returning on the given Tick. This
209 * function may return curTick() if the CPU should run on the
210 * current cycle.
211 * @param begin_tick The tick that the event is completing on.
212 */
213 Tick nextCycle(Tick begin_tick);
214
215 TheISA::MicrocodeRom microcodeRom;
216
217 protected:
218 TheISA::Interrupts *interrupts;
219
220 public:
221 TheISA::Interrupts *
222 getInterruptController()
223 {
224 return interrupts;
225 }
226
227 virtual void wakeup() = 0;
228
229 void
230 postInterrupt(int int_num, int index)
231 {
232 interrupts->post(int_num, index);
233 if (FullSystem)
234 wakeup();
235 }
236
237 void
238 clearInterrupt(int int_num, int index)
239 {
240 interrupts->clear(int_num, index);
241 }
242
243 void
244 clearInterrupts()
245 {
246 interrupts->clearAll();
247 }
248
249 bool
250 checkInterrupts(ThreadContext *tc) const
251 {
252 return FullSystem && interrupts->checkInterrupts(tc);
253 }
254
255 class ProfileEvent : public Event
256 {
257 private:
258 BaseCPU *cpu;
259 Tick interval;
260
261 public:
262 ProfileEvent(BaseCPU *cpu, Tick interval);
263 void process();
264 };
265 ProfileEvent *profileEvent;
266
267 protected:
268 std::vector<ThreadContext *> threadContexts;
269 std::vector<TheISA::Predecoder *> predecoders;
270
271 Trace::InstTracer * tracer;
272
273 public:
274
275 // Mask to align PCs to MachInst sized boundaries
276 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
277
278 /// Provide access to the tracer pointer
279 Trace::InstTracer * getTracer() { return tracer; }
280
281 /// Notify the CPU that the indicated context is now active. The
282 /// delay parameter indicates the number of ticks to wait before
283 /// executing (typically 0 or 1).
284 virtual void activateContext(ThreadID thread_num, int delay) {}
285
286 /// Notify the CPU that the indicated context is now suspended.
287 virtual void suspendContext(ThreadID thread_num) {}
288
289 /// Notify the CPU that the indicated context is now deallocated.
290 virtual void deallocateContext(ThreadID thread_num) {}
291
292 /// Notify the CPU that the indicated context is now halted.
293 virtual void haltContext(ThreadID thread_num) {}
294
295 /// Given a Thread Context pointer return the thread num
296 int findContext(ThreadContext *tc);
297
298 /// Given a thread num get tho thread context for it
299 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
300
301 public:
302 typedef BaseCPUParams Params;
303 const Params *params() const
304 { return reinterpret_cast<const Params *>(_params); }
305 BaseCPU(Params *params);
306 virtual ~BaseCPU();
307
308 virtual void init();
309 virtual void startup();
310 virtual void regStats();
311
312 virtual void activateWhenReady(ThreadID tid) {};
313
314 void registerThreadContexts();
315
316 /// Prepare for another CPU to take over execution. When it is
317 /// is ready (drained pipe) it signals the sampler.
318 virtual void switchOut();
319
320 /// Take over execution from the given CPU. Used for warm-up and
321 /// sampling.
322 virtual void takeOverFrom(BaseCPU *);
323
324 /**
325 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
326 * This is a constant for the duration of the simulation.
327 */
328 ThreadID numThreads;
329
330 /**
331 * Vector of per-thread instruction-based event queues. Used for
332 * scheduling events based on number of instructions committed by
333 * a particular thread.
334 */
335 EventQueue **comInstEventQueue;
336
337 /**
338 * Vector of per-thread load-based event queues. Used for
339 * scheduling events based on number of loads committed by
340 *a particular thread.
341 */
342 EventQueue **comLoadEventQueue;
343
344 System *system;
345
346 Tick phase;
347
348 /**
349 * Serialize this object to the given output stream.
350 * @param os The stream to serialize to.
351 */
352 virtual void serialize(std::ostream &os);
353
354 /**
355 * Reconstruct the state of this object from a checkpoint.
356 * @param cp The checkpoint use.
357 * @param section The section name of this object
358 */
359 virtual void unserialize(Checkpoint *cp, const std::string §ion);
360
361 /**
362 * Return pointer to CPU's branch predictor (NULL if none).
363 * @return Branch predictor pointer.
364 */
365 virtual BranchPred *getBranchPred() { return NULL; };
366
367 virtual Counter totalInsts() const = 0;
368
369 virtual Counter totalOps() const = 0;
370
371 // Function tracing
372 private:
373 bool functionTracingEnabled;
374 std::ostream *functionTraceStream;
375 Addr currentFunctionStart;
376 Addr currentFunctionEnd;
377 Tick functionEntryTick;
378 void enableFunctionTrace();
379 void traceFunctionsInternal(Addr pc);
380
381 private:
382 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
383
384 public:
385 void traceFunctions(Addr pc)
386 {
387 if (functionTracingEnabled)
388 traceFunctionsInternal(pc);
389 }
390
391 static int numSimulatedCPUs() { return cpuList.size(); }
392 static Counter numSimulatedInsts()
393 {
394 Counter total = 0;
395
396 int size = cpuList.size();
397 for (int i = 0; i < size; ++i)
398 total += cpuList[i]->totalInsts();
399
400 return total;
401 }
402
403 static Counter numSimulatedOps()
404 {
405 Counter total = 0;
406
407 int size = cpuList.size();
408 for (int i = 0; i < size; ++i)
409 total += cpuList[i]->totalOps();
410
411 return total;
412 }
413
414 public:
415 // Number of CPU cycles simulated
416 Stats::Scalar numCycles;
417 Stats::Scalar numWorkItemsStarted;
418 Stats::Scalar numWorkItemsCompleted;
419};
420
421#endif // __CPU_BASE_HH__
|