1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "base/statistics.hh"
39#include "config/full_system.hh"
40#include "sim/eventq.hh"
41#include "sim/insttracer.hh"
42#include "mem/mem_object.hh"
43
44#if FULL_SYSTEM
45#include "arch/interrupts.hh"
46#endif
47
48class BaseCPUParams;
49class BranchPred;
50class CheckerCPU;
51class ThreadContext;
52class System;
53class Port;
54
55namespace TheISA
56{
57 class Predecoder;
58}
59
60class CPUProgressEvent : public Event
61{
62 protected:
63 Tick interval;
64 Counter lastNumInst;
65 BaseCPU *cpu;
66
67 public:
68 CPUProgressEvent(BaseCPU *_cpu, Tick ival);
69
70 void process();
71
72 virtual const char *description() const;
73};
74
75class BaseCPU : public MemObject
76{
77 protected:
78 // CPU's clock period in terms of the number of ticks of curTime.
79 Tick clock;
80 // @todo remove me after debugging with legion done
81 Tick instCnt;
82
83 public:
84// Tick currentTick;
85 inline Tick frequency() const { return Clock::Frequency / clock; }
86 inline Tick ticks(int numCycles) const { return clock * numCycles; }
87 inline Tick curCycle() const { return curTick / clock; }
88 inline Tick tickToCycles(Tick val) const { return val / clock; }
89 // @todo remove me after debugging with legion done
90 Tick instCount() { return instCnt; }
91
92 /** The next cycle the CPU should be scheduled, given a cache
93 * access or quiesce event returning on this cycle. This function
94 * may return curTick if the CPU should run on the current cycle.
95 */
96 Tick nextCycle();
97
98 /** The next cycle the CPU should be scheduled, given a cache
99 * access or quiesce event returning on the given Tick. This
100 * function may return curTick if the CPU should run on the
101 * current cycle.
102 * @param begin_tick The tick that the event is completing on.
103 */
104 Tick nextCycle(Tick begin_tick);
105
106#if FULL_SYSTEM
107 protected:
108// uint64_t interrupts[TheISA::NumInterruptLevels];
109// uint64_t intstatus;
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "base/statistics.hh"
39#include "config/full_system.hh"
40#include "sim/eventq.hh"
41#include "sim/insttracer.hh"
42#include "mem/mem_object.hh"
43
44#if FULL_SYSTEM
45#include "arch/interrupts.hh"
46#endif
47
48class BaseCPUParams;
49class BranchPred;
50class CheckerCPU;
51class ThreadContext;
52class System;
53class Port;
54
55namespace TheISA
56{
57 class Predecoder;
58}
59
60class CPUProgressEvent : public Event
61{
62 protected:
63 Tick interval;
64 Counter lastNumInst;
65 BaseCPU *cpu;
66
67 public:
68 CPUProgressEvent(BaseCPU *_cpu, Tick ival);
69
70 void process();
71
72 virtual const char *description() const;
73};
74
75class BaseCPU : public MemObject
76{
77 protected:
78 // CPU's clock period in terms of the number of ticks of curTime.
79 Tick clock;
80 // @todo remove me after debugging with legion done
81 Tick instCnt;
82
83 public:
84// Tick currentTick;
85 inline Tick frequency() const { return Clock::Frequency / clock; }
86 inline Tick ticks(int numCycles) const { return clock * numCycles; }
87 inline Tick curCycle() const { return curTick / clock; }
88 inline Tick tickToCycles(Tick val) const { return val / clock; }
89 // @todo remove me after debugging with legion done
90 Tick instCount() { return instCnt; }
91
92 /** The next cycle the CPU should be scheduled, given a cache
93 * access or quiesce event returning on this cycle. This function
94 * may return curTick if the CPU should run on the current cycle.
95 */
96 Tick nextCycle();
97
98 /** The next cycle the CPU should be scheduled, given a cache
99 * access or quiesce event returning on the given Tick. This
100 * function may return curTick if the CPU should run on the
101 * current cycle.
102 * @param begin_tick The tick that the event is completing on.
103 */
104 Tick nextCycle(Tick begin_tick);
105
106#if FULL_SYSTEM
107 protected:
108// uint64_t interrupts[TheISA::NumInterruptLevels];
109// uint64_t intstatus;
|
117 }
118
119 virtual void post_interrupt(int int_num, int index);
120 virtual void clear_interrupt(int int_num, int index);
121 virtual void clear_interrupts();
122
123 bool check_interrupts(ThreadContext * tc) const
| 117 }
118
119 virtual void post_interrupt(int int_num, int index);
120 virtual void clear_interrupt(int int_num, int index);
121 virtual void clear_interrupts();
122
123 bool check_interrupts(ThreadContext * tc) const
|
125
126 class ProfileEvent : public Event
127 {
128 private:
129 BaseCPU *cpu;
130 Tick interval;
131
132 public:
133 ProfileEvent(BaseCPU *cpu, Tick interval);
134 void process();
135 };
136 ProfileEvent *profileEvent;
137#endif
138
139 protected:
140 std::vector<ThreadContext *> threadContexts;
141 std::vector<TheISA::Predecoder *> predecoders;
142
143 Trace::InstTracer * tracer;
144
145 public:
146
147 /// Provide access to the tracer pointer
148 Trace::InstTracer * getTracer() { return tracer; }
149
150 /// Notify the CPU that the indicated context is now active. The
151 /// delay parameter indicates the number of ticks to wait before
152 /// executing (typically 0 or 1).
153 virtual void activateContext(int thread_num, int delay) {}
154
155 /// Notify the CPU that the indicated context is now suspended.
156 virtual void suspendContext(int thread_num) {}
157
158 /// Notify the CPU that the indicated context is now deallocated.
159 virtual void deallocateContext(int thread_num) {}
160
161 /// Notify the CPU that the indicated context is now halted.
162 virtual void haltContext(int thread_num) {}
163
164 /// Given a Thread Context pointer return the thread num
165 int findContext(ThreadContext *tc);
166
167 /// Given a thread num get tho thread context for it
168 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
169
170 public:
171 typedef BaseCPUParams Params;
172 const Params *params() const
173 { return reinterpret_cast<const Params *>(_params); }
174 BaseCPU(Params *params);
175 virtual ~BaseCPU();
176
177 virtual void init();
178 virtual void startup();
179 virtual void regStats();
180
181 virtual void activateWhenReady(int tid) {};
182
183 void registerThreadContexts();
184
185 /// Prepare for another CPU to take over execution. When it is
186 /// is ready (drained pipe) it signals the sampler.
187 virtual void switchOut();
188
189 /// Take over execution from the given CPU. Used for warm-up and
190 /// sampling.
191 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
192
193 /**
194 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
195 * This is a constant for the duration of the simulation.
196 */
197 int number_of_threads;
198
199 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
200
201 /**
202 * Vector of per-thread instruction-based event queues. Used for
203 * scheduling events based on number of instructions committed by
204 * a particular thread.
205 */
206 EventQueue **comInstEventQueue;
207
208 /**
209 * Vector of per-thread load-based event queues. Used for
210 * scheduling events based on number of loads committed by
211 *a particular thread.
212 */
213 EventQueue **comLoadEventQueue;
214
215 System *system;
216
217 Tick phase;
218
219#if FULL_SYSTEM
220 /**
221 * Serialize this object to the given output stream.
222 * @param os The stream to serialize to.
223 */
224 virtual void serialize(std::ostream &os);
225
226 /**
227 * Reconstruct the state of this object from a checkpoint.
228 * @param cp The checkpoint use.
229 * @param section The section name of this object
230 */
231 virtual void unserialize(Checkpoint *cp, const std::string §ion);
232
233#endif
234
235 /**
236 * Return pointer to CPU's branch predictor (NULL if none).
237 * @return Branch predictor pointer.
238 */
239 virtual BranchPred *getBranchPred() { return NULL; };
240
241 virtual Counter totalInstructions() const { return 0; }
242
243 // Function tracing
244 private:
245 bool functionTracingEnabled;
246 std::ostream *functionTraceStream;
247 Addr currentFunctionStart;
248 Addr currentFunctionEnd;
249 Tick functionEntryTick;
250 void enableFunctionTrace();
251 void traceFunctionsInternal(Addr pc);
252
253 protected:
254 void traceFunctions(Addr pc)
255 {
256 if (functionTracingEnabled)
257 traceFunctionsInternal(pc);
258 }
259
260 private:
261 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
262
263 public:
264 static int numSimulatedCPUs() { return cpuList.size(); }
265 static Counter numSimulatedInstructions()
266 {
267 Counter total = 0;
268
269 int size = cpuList.size();
270 for (int i = 0; i < size; ++i)
271 total += cpuList[i]->totalInstructions();
272
273 return total;
274 }
275
276 public:
277 // Number of CPU cycles simulated
278 Stats::Scalar<> numCycles;
279};
280
281#endif // __CPU_BASE_HH__
| 125
126 class ProfileEvent : public Event
127 {
128 private:
129 BaseCPU *cpu;
130 Tick interval;
131
132 public:
133 ProfileEvent(BaseCPU *cpu, Tick interval);
134 void process();
135 };
136 ProfileEvent *profileEvent;
137#endif
138
139 protected:
140 std::vector<ThreadContext *> threadContexts;
141 std::vector<TheISA::Predecoder *> predecoders;
142
143 Trace::InstTracer * tracer;
144
145 public:
146
147 /// Provide access to the tracer pointer
148 Trace::InstTracer * getTracer() { return tracer; }
149
150 /// Notify the CPU that the indicated context is now active. The
151 /// delay parameter indicates the number of ticks to wait before
152 /// executing (typically 0 or 1).
153 virtual void activateContext(int thread_num, int delay) {}
154
155 /// Notify the CPU that the indicated context is now suspended.
156 virtual void suspendContext(int thread_num) {}
157
158 /// Notify the CPU that the indicated context is now deallocated.
159 virtual void deallocateContext(int thread_num) {}
160
161 /// Notify the CPU that the indicated context is now halted.
162 virtual void haltContext(int thread_num) {}
163
164 /// Given a Thread Context pointer return the thread num
165 int findContext(ThreadContext *tc);
166
167 /// Given a thread num get tho thread context for it
168 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
169
170 public:
171 typedef BaseCPUParams Params;
172 const Params *params() const
173 { return reinterpret_cast<const Params *>(_params); }
174 BaseCPU(Params *params);
175 virtual ~BaseCPU();
176
177 virtual void init();
178 virtual void startup();
179 virtual void regStats();
180
181 virtual void activateWhenReady(int tid) {};
182
183 void registerThreadContexts();
184
185 /// Prepare for another CPU to take over execution. When it is
186 /// is ready (drained pipe) it signals the sampler.
187 virtual void switchOut();
188
189 /// Take over execution from the given CPU. Used for warm-up and
190 /// sampling.
191 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
192
193 /**
194 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
195 * This is a constant for the duration of the simulation.
196 */
197 int number_of_threads;
198
199 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
200
201 /**
202 * Vector of per-thread instruction-based event queues. Used for
203 * scheduling events based on number of instructions committed by
204 * a particular thread.
205 */
206 EventQueue **comInstEventQueue;
207
208 /**
209 * Vector of per-thread load-based event queues. Used for
210 * scheduling events based on number of loads committed by
211 *a particular thread.
212 */
213 EventQueue **comLoadEventQueue;
214
215 System *system;
216
217 Tick phase;
218
219#if FULL_SYSTEM
220 /**
221 * Serialize this object to the given output stream.
222 * @param os The stream to serialize to.
223 */
224 virtual void serialize(std::ostream &os);
225
226 /**
227 * Reconstruct the state of this object from a checkpoint.
228 * @param cp The checkpoint use.
229 * @param section The section name of this object
230 */
231 virtual void unserialize(Checkpoint *cp, const std::string §ion);
232
233#endif
234
235 /**
236 * Return pointer to CPU's branch predictor (NULL if none).
237 * @return Branch predictor pointer.
238 */
239 virtual BranchPred *getBranchPred() { return NULL; };
240
241 virtual Counter totalInstructions() const { return 0; }
242
243 // Function tracing
244 private:
245 bool functionTracingEnabled;
246 std::ostream *functionTraceStream;
247 Addr currentFunctionStart;
248 Addr currentFunctionEnd;
249 Tick functionEntryTick;
250 void enableFunctionTrace();
251 void traceFunctionsInternal(Addr pc);
252
253 protected:
254 void traceFunctions(Addr pc)
255 {
256 if (functionTracingEnabled)
257 traceFunctionsInternal(pc);
258 }
259
260 private:
261 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
262
263 public:
264 static int numSimulatedCPUs() { return cpuList.size(); }
265 static Counter numSimulatedInstructions()
266 {
267 Counter total = 0;
268
269 int size = cpuList.size();
270 for (int i = 0; i < size; ++i)
271 total += cpuList[i]->totalInstructions();
272
273 return total;
274 }
275
276 public:
277 // Number of CPU cycles simulated
278 Stats::Scalar<> numCycles;
279};
280
281#endif // __CPU_BASE_HH__
|