1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "arch/isa_traits.hh" 38#include "base/statistics.hh" 39#include "config/full_system.hh" 40#include "sim/eventq.hh" 41#include "sim/insttracer.hh" 42#include "mem/mem_object.hh" 43 44#if FULL_SYSTEM 45#include "arch/interrupts.hh" 46#endif 47 48class BaseCPUParams; 49class BranchPred; 50class CheckerCPU; 51class ThreadContext; 52class System; 53class Port; 54 55namespace TheISA 56{ 57 class Predecoder; 58} 59 60class CPUProgressEvent : public Event 61{ 62 protected: 63 Tick interval; 64 Counter lastNumInst; 65 BaseCPU *cpu; 66 67 public: 68 CPUProgressEvent(BaseCPU *_cpu, Tick ival); 69 70 void process(); 71 72 virtual const char *description() const; 73}; 74 75class BaseCPU : public MemObject 76{ 77 protected: 78 // CPU's clock period in terms of the number of ticks of curTime. 79 Tick clock; 80 // @todo remove me after debugging with legion done 81 Tick instCnt; 82 83 public: 84// Tick currentTick; 85 inline Tick frequency() const { return Clock::Frequency / clock; } 86 inline Tick ticks(int numCycles) const { return clock * numCycles; } 87 inline Tick curCycle() const { return curTick / clock; } 88 inline Tick tickToCycles(Tick val) const { return val / clock; } 89 // @todo remove me after debugging with legion done 90 Tick instCount() { return instCnt; } 91 92 /** The next cycle the CPU should be scheduled, given a cache 93 * access or quiesce event returning on this cycle. This function 94 * may return curTick if the CPU should run on the current cycle. 95 */ 96 Tick nextCycle(); 97 98 /** The next cycle the CPU should be scheduled, given a cache 99 * access or quiesce event returning on the given Tick. This 100 * function may return curTick if the CPU should run on the 101 * current cycle. 102 * @param begin_tick The tick that the event is completing on. 103 */ 104 Tick nextCycle(Tick begin_tick); 105 106#if FULL_SYSTEM 107 protected: 108// uint64_t interrupts[TheISA::NumInterruptLevels]; 109// uint64_t intstatus; 110 TheISA::Interrupts interrupts; 111 112 public:
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "arch/isa_traits.hh" 38#include "base/statistics.hh" 39#include "config/full_system.hh" 40#include "sim/eventq.hh" 41#include "sim/insttracer.hh" 42#include "mem/mem_object.hh" 43 44#if FULL_SYSTEM 45#include "arch/interrupts.hh" 46#endif 47 48class BaseCPUParams; 49class BranchPred; 50class CheckerCPU; 51class ThreadContext; 52class System; 53class Port; 54 55namespace TheISA 56{ 57 class Predecoder; 58} 59 60class CPUProgressEvent : public Event 61{ 62 protected: 63 Tick interval; 64 Counter lastNumInst; 65 BaseCPU *cpu; 66 67 public: 68 CPUProgressEvent(BaseCPU *_cpu, Tick ival); 69 70 void process(); 71 72 virtual const char *description() const; 73}; 74 75class BaseCPU : public MemObject 76{ 77 protected: 78 // CPU's clock period in terms of the number of ticks of curTime. 79 Tick clock; 80 // @todo remove me after debugging with legion done 81 Tick instCnt; 82 83 public: 84// Tick currentTick; 85 inline Tick frequency() const { return Clock::Frequency / clock; } 86 inline Tick ticks(int numCycles) const { return clock * numCycles; } 87 inline Tick curCycle() const { return curTick / clock; } 88 inline Tick tickToCycles(Tick val) const { return val / clock; } 89 // @todo remove me after debugging with legion done 90 Tick instCount() { return instCnt; } 91 92 /** The next cycle the CPU should be scheduled, given a cache 93 * access or quiesce event returning on this cycle. This function 94 * may return curTick if the CPU should run on the current cycle. 95 */ 96 Tick nextCycle(); 97 98 /** The next cycle the CPU should be scheduled, given a cache 99 * access or quiesce event returning on the given Tick. This 100 * function may return curTick if the CPU should run on the 101 * current cycle. 102 * @param begin_tick The tick that the event is completing on. 103 */ 104 Tick nextCycle(Tick begin_tick); 105 106#if FULL_SYSTEM 107 protected: 108// uint64_t interrupts[TheISA::NumInterruptLevels]; 109// uint64_t intstatus; 110 TheISA::Interrupts interrupts; 111 112 public:
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113 virtual void post_interrupt(int int_num, int index); 114 virtual void clear_interrupt(int int_num, int index); 115 virtual void clear_interrupts(); 116 virtual uint64_t get_interrupts(int int_num); 117 118 bool check_interrupts(ThreadContext * tc) const 119 { return interrupts.check_interrupts(tc); } 120 121 class ProfileEvent : public Event 122 { 123 private: 124 BaseCPU *cpu; 125 Tick interval; 126 127 public: 128 ProfileEvent(BaseCPU *cpu, Tick interval); 129 void process(); 130 }; 131 ProfileEvent *profileEvent; 132#endif 133 134 protected: 135 std::vector<ThreadContext *> threadContexts; 136 std::vector<TheISA::Predecoder *> predecoders; 137 138 Trace::InstTracer * tracer; 139 140 public: 141 142 /// Provide access to the tracer pointer 143 Trace::InstTracer * getTracer() { return tracer; } 144 145 /// Notify the CPU that the indicated context is now active. The 146 /// delay parameter indicates the number of ticks to wait before 147 /// executing (typically 0 or 1). 148 virtual void activateContext(int thread_num, int delay) {} 149 150 /// Notify the CPU that the indicated context is now suspended. 151 virtual void suspendContext(int thread_num) {} 152 153 /// Notify the CPU that the indicated context is now deallocated. 154 virtual void deallocateContext(int thread_num) {} 155 156 /// Notify the CPU that the indicated context is now halted. 157 virtual void haltContext(int thread_num) {} 158 159 /// Given a Thread Context pointer return the thread num 160 int findContext(ThreadContext *tc); 161 162 /// Given a thread num get tho thread context for it 163 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 164 165 public: 166 typedef BaseCPUParams Params; 167 const Params *params() const 168 { return reinterpret_cast<const Params *>(_params); } 169 BaseCPU(Params *params); 170 virtual ~BaseCPU(); 171 172 virtual void init(); 173 virtual void startup(); 174 virtual void regStats(); 175 176 virtual void activateWhenReady(int tid) {}; 177 178 void registerThreadContexts(); 179 180 /// Prepare for another CPU to take over execution. When it is 181 /// is ready (drained pipe) it signals the sampler. 182 virtual void switchOut(); 183 184 /// Take over execution from the given CPU. Used for warm-up and 185 /// sampling. 186 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 187 188 /** 189 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 190 * This is a constant for the duration of the simulation. 191 */ 192 int number_of_threads; 193 194 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 195 196 /** 197 * Vector of per-thread instruction-based event queues. Used for 198 * scheduling events based on number of instructions committed by 199 * a particular thread. 200 */ 201 EventQueue **comInstEventQueue; 202 203 /** 204 * Vector of per-thread load-based event queues. Used for 205 * scheduling events based on number of loads committed by 206 *a particular thread. 207 */ 208 EventQueue **comLoadEventQueue; 209 210 System *system; 211 212 Tick phase; 213 214#if FULL_SYSTEM 215 /** 216 * Serialize this object to the given output stream. 217 * @param os The stream to serialize to. 218 */ 219 virtual void serialize(std::ostream &os); 220 221 /** 222 * Reconstruct the state of this object from a checkpoint. 223 * @param cp The checkpoint use. 224 * @param section The section name of this object 225 */ 226 virtual void unserialize(Checkpoint *cp, const std::string §ion); 227 228#endif 229 230 /** 231 * Return pointer to CPU's branch predictor (NULL if none). 232 * @return Branch predictor pointer. 233 */ 234 virtual BranchPred *getBranchPred() { return NULL; }; 235 236 virtual Counter totalInstructions() const { return 0; } 237 238 // Function tracing 239 private: 240 bool functionTracingEnabled; 241 std::ostream *functionTraceStream; 242 Addr currentFunctionStart; 243 Addr currentFunctionEnd; 244 Tick functionEntryTick; 245 void enableFunctionTrace(); 246 void traceFunctionsInternal(Addr pc); 247 248 protected: 249 void traceFunctions(Addr pc) 250 { 251 if (functionTracingEnabled) 252 traceFunctionsInternal(pc); 253 } 254 255 private: 256 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 257 258 public: 259 static int numSimulatedCPUs() { return cpuList.size(); } 260 static Counter numSimulatedInstructions() 261 { 262 Counter total = 0; 263 264 int size = cpuList.size(); 265 for (int i = 0; i < size; ++i) 266 total += cpuList[i]->totalInstructions(); 267 268 return total; 269 } 270 271 public: 272 // Number of CPU cycles simulated 273 Stats::Scalar<> numCycles; 274}; 275 276#endif // __CPU_BASE_HH__
| 119 virtual void post_interrupt(int int_num, int index); 120 virtual void clear_interrupt(int int_num, int index); 121 virtual void clear_interrupts(); 122 virtual uint64_t get_interrupts(int int_num); 123 124 bool check_interrupts(ThreadContext * tc) const 125 { return interrupts.check_interrupts(tc); } 126 127 class ProfileEvent : public Event 128 { 129 private: 130 BaseCPU *cpu; 131 Tick interval; 132 133 public: 134 ProfileEvent(BaseCPU *cpu, Tick interval); 135 void process(); 136 }; 137 ProfileEvent *profileEvent; 138#endif 139 140 protected: 141 std::vector<ThreadContext *> threadContexts; 142 std::vector<TheISA::Predecoder *> predecoders; 143 144 Trace::InstTracer * tracer; 145 146 public: 147 148 /// Provide access to the tracer pointer 149 Trace::InstTracer * getTracer() { return tracer; } 150 151 /// Notify the CPU that the indicated context is now active. The 152 /// delay parameter indicates the number of ticks to wait before 153 /// executing (typically 0 or 1). 154 virtual void activateContext(int thread_num, int delay) {} 155 156 /// Notify the CPU that the indicated context is now suspended. 157 virtual void suspendContext(int thread_num) {} 158 159 /// Notify the CPU that the indicated context is now deallocated. 160 virtual void deallocateContext(int thread_num) {} 161 162 /// Notify the CPU that the indicated context is now halted. 163 virtual void haltContext(int thread_num) {} 164 165 /// Given a Thread Context pointer return the thread num 166 int findContext(ThreadContext *tc); 167 168 /// Given a thread num get tho thread context for it 169 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 170 171 public: 172 typedef BaseCPUParams Params; 173 const Params *params() const 174 { return reinterpret_cast<const Params *>(_params); } 175 BaseCPU(Params *params); 176 virtual ~BaseCPU(); 177 178 virtual void init(); 179 virtual void startup(); 180 virtual void regStats(); 181 182 virtual void activateWhenReady(int tid) {}; 183 184 void registerThreadContexts(); 185 186 /// Prepare for another CPU to take over execution. When it is 187 /// is ready (drained pipe) it signals the sampler. 188 virtual void switchOut(); 189 190 /// Take over execution from the given CPU. Used for warm-up and 191 /// sampling. 192 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 193 194 /** 195 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 196 * This is a constant for the duration of the simulation. 197 */ 198 int number_of_threads; 199 200 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 201 202 /** 203 * Vector of per-thread instruction-based event queues. Used for 204 * scheduling events based on number of instructions committed by 205 * a particular thread. 206 */ 207 EventQueue **comInstEventQueue; 208 209 /** 210 * Vector of per-thread load-based event queues. Used for 211 * scheduling events based on number of loads committed by 212 *a particular thread. 213 */ 214 EventQueue **comLoadEventQueue; 215 216 System *system; 217 218 Tick phase; 219 220#if FULL_SYSTEM 221 /** 222 * Serialize this object to the given output stream. 223 * @param os The stream to serialize to. 224 */ 225 virtual void serialize(std::ostream &os); 226 227 /** 228 * Reconstruct the state of this object from a checkpoint. 229 * @param cp The checkpoint use. 230 * @param section The section name of this object 231 */ 232 virtual void unserialize(Checkpoint *cp, const std::string §ion); 233 234#endif 235 236 /** 237 * Return pointer to CPU's branch predictor (NULL if none). 238 * @return Branch predictor pointer. 239 */ 240 virtual BranchPred *getBranchPred() { return NULL; }; 241 242 virtual Counter totalInstructions() const { return 0; } 243 244 // Function tracing 245 private: 246 bool functionTracingEnabled; 247 std::ostream *functionTraceStream; 248 Addr currentFunctionStart; 249 Addr currentFunctionEnd; 250 Tick functionEntryTick; 251 void enableFunctionTrace(); 252 void traceFunctionsInternal(Addr pc); 253 254 protected: 255 void traceFunctions(Addr pc) 256 { 257 if (functionTracingEnabled) 258 traceFunctionsInternal(pc); 259 } 260 261 private: 262 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 263 264 public: 265 static int numSimulatedCPUs() { return cpuList.size(); } 266 static Counter numSimulatedInstructions() 267 { 268 Counter total = 0; 269 270 int size = cpuList.size(); 271 for (int i = 0; i < size; ++i) 272 total += cpuList[i]->totalInstructions(); 273 274 return total; 275 } 276 277 public: 278 // Number of CPU cycles simulated 279 Stats::Scalar<> numCycles; 280}; 281 282#endif // __CPU_BASE_HH__
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