1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "sim/eventq.hh" 40#include "mem/mem_object.hh" 41#include "arch/isa_traits.hh" 42 43#if FULL_SYSTEM 44#include "arch/interrupts.hh" 45#endif 46 47class BranchPred; 48class CheckerCPU; 49class ThreadContext; 50class System; 51class Port; 52 53class CPUProgressEvent : public Event 54{ 55 protected: 56 Tick interval; 57 Counter lastNumInst; 58 BaseCPU *cpu; 59 60 public: 61 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 62 63 void process(); 64 65 virtual const char *description(); 66}; 67 68class BaseCPU : public MemObject 69{ 70 protected: 71 // CPU's clock period in terms of the number of ticks of curTime. 72 Tick clock; 73 74 public: 75// Tick currentTick; 76 inline Tick frequency() const { return Clock::Frequency / clock; } 77 inline Tick cycles(int numCycles) const { return clock * numCycles; } 78 inline Tick curCycle() const { return curTick / clock; } 79 80 /** The next cycle the CPU should be scheduled, given a cache 81 * access or quiesce event returning on this cycle. This function 82 * may return curTick if the CPU should run on the current cycle. 83 */ 84 Tick nextCycle(); 85 86 /** The next cycle the CPU should be scheduled, given a cache 87 * access or quiesce event returning on the given Tick. This 88 * function may return curTick if the CPU should run on the 89 * current cycle. 90 * @param begin_tick The tick that the event is completing on. 91 */ 92 Tick nextCycle(Tick begin_tick); 93 94#if FULL_SYSTEM 95 protected: 96// uint64_t interrupts[TheISA::NumInterruptLevels]; 97// uint64_t intstatus; 98 TheISA::Interrupts interrupts; 99 100 public: 101 virtual void post_interrupt(int int_num, int index); 102 virtual void clear_interrupt(int int_num, int index); 103 virtual void clear_interrupts(); 104 bool checkInterrupts; 105 106 bool check_interrupts(ThreadContext * tc) const 107 { return interrupts.check_interrupts(tc); } 108 109 class ProfileEvent : public Event 110 { 111 private: 112 BaseCPU *cpu; 113 int interval; 114 115 public: 116 ProfileEvent(BaseCPU *cpu, int interval); 117 void process(); 118 }; 119 ProfileEvent *profileEvent; 120#endif 121 122 protected: 123 std::vector<ThreadContext *> threadContexts; 124 125 public: 126 127 /// Notify the CPU that the indicated context is now active. The 128 /// delay parameter indicates the number of ticks to wait before 129 /// executing (typically 0 or 1). 130 virtual void activateContext(int thread_num, int delay) {} 131 132 /// Notify the CPU that the indicated context is now suspended. 133 virtual void suspendContext(int thread_num) {} 134 135 /// Notify the CPU that the indicated context is now deallocated. 136 virtual void deallocateContext(int thread_num) {} 137 138 /// Notify the CPU that the indicated context is now halted. 139 virtual void haltContext(int thread_num) {} 140 141 public: 142 struct Params 143 { 144 std::string name; 145 int numberOfThreads; 146 bool deferRegistration; 147 Counter max_insts_any_thread; 148 Counter max_insts_all_threads; 149 Counter max_loads_any_thread; 150 Counter max_loads_all_threads; 151 Tick clock; 152 bool functionTrace; 153 Tick functionTraceStart; 154 System *system; 155 int cpu_id;
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "sim/eventq.hh" 40#include "mem/mem_object.hh" 41#include "arch/isa_traits.hh" 42 43#if FULL_SYSTEM 44#include "arch/interrupts.hh" 45#endif 46 47class BranchPred; 48class CheckerCPU; 49class ThreadContext; 50class System; 51class Port; 52 53class CPUProgressEvent : public Event 54{ 55 protected: 56 Tick interval; 57 Counter lastNumInst; 58 BaseCPU *cpu; 59 60 public: 61 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 62 63 void process(); 64 65 virtual const char *description(); 66}; 67 68class BaseCPU : public MemObject 69{ 70 protected: 71 // CPU's clock period in terms of the number of ticks of curTime. 72 Tick clock; 73 74 public: 75// Tick currentTick; 76 inline Tick frequency() const { return Clock::Frequency / clock; } 77 inline Tick cycles(int numCycles) const { return clock * numCycles; } 78 inline Tick curCycle() const { return curTick / clock; } 79 80 /** The next cycle the CPU should be scheduled, given a cache 81 * access or quiesce event returning on this cycle. This function 82 * may return curTick if the CPU should run on the current cycle. 83 */ 84 Tick nextCycle(); 85 86 /** The next cycle the CPU should be scheduled, given a cache 87 * access or quiesce event returning on the given Tick. This 88 * function may return curTick if the CPU should run on the 89 * current cycle. 90 * @param begin_tick The tick that the event is completing on. 91 */ 92 Tick nextCycle(Tick begin_tick); 93 94#if FULL_SYSTEM 95 protected: 96// uint64_t interrupts[TheISA::NumInterruptLevels]; 97// uint64_t intstatus; 98 TheISA::Interrupts interrupts; 99 100 public: 101 virtual void post_interrupt(int int_num, int index); 102 virtual void clear_interrupt(int int_num, int index); 103 virtual void clear_interrupts(); 104 bool checkInterrupts; 105 106 bool check_interrupts(ThreadContext * tc) const 107 { return interrupts.check_interrupts(tc); } 108 109 class ProfileEvent : public Event 110 { 111 private: 112 BaseCPU *cpu; 113 int interval; 114 115 public: 116 ProfileEvent(BaseCPU *cpu, int interval); 117 void process(); 118 }; 119 ProfileEvent *profileEvent; 120#endif 121 122 protected: 123 std::vector<ThreadContext *> threadContexts; 124 125 public: 126 127 /// Notify the CPU that the indicated context is now active. The 128 /// delay parameter indicates the number of ticks to wait before 129 /// executing (typically 0 or 1). 130 virtual void activateContext(int thread_num, int delay) {} 131 132 /// Notify the CPU that the indicated context is now suspended. 133 virtual void suspendContext(int thread_num) {} 134 135 /// Notify the CPU that the indicated context is now deallocated. 136 virtual void deallocateContext(int thread_num) {} 137 138 /// Notify the CPU that the indicated context is now halted. 139 virtual void haltContext(int thread_num) {} 140 141 public: 142 struct Params 143 { 144 std::string name; 145 int numberOfThreads; 146 bool deferRegistration; 147 Counter max_insts_any_thread; 148 Counter max_insts_all_threads; 149 Counter max_loads_any_thread; 150 Counter max_loads_all_threads; 151 Tick clock; 152 bool functionTrace; 153 Tick functionTraceStart; 154 System *system; 155 int cpu_id;
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