1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "sim/eventq.hh"
40#include "mem/mem_object.hh"
41#include "arch/isa_traits.hh"
42
43class BranchPred;
44class CheckerCPU;
45class ThreadContext;
46class System;
47class Port;
48
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "sim/eventq.hh"
40#include "mem/mem_object.hh"
41#include "arch/isa_traits.hh"
42
43class BranchPred;
44class CheckerCPU;
45class ThreadContext;
46class System;
47class Port;
48
|
| 49class CPUProgressEvent : public Event
50{
51 protected:
52 Tick interval;
53 Counter lastNumInst;
54 BaseCPU *cpu;
55
56 public:
57 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu)
58 : Event(q, Event::Stat_Event_Pri), interval(ival), lastNumInst(0), cpu(_cpu)
59 { schedule(curTick + interval); }
60
61 void process();
62
63 virtual const char *description();
64};
65
|
49class BaseCPU : public MemObject
50{
51 protected:
52 // CPU's clock period in terms of the number of ticks of curTime.
53 Tick clock;
54
55 public:
| 66class BaseCPU : public MemObject
67{
68 protected:
69 // CPU's clock period in terms of the number of ticks of curTime.
70 Tick clock;
71
72 public:
|
| 73// Tick currentTick;
|
56 inline Tick frequency() const { return Clock::Frequency / clock; }
57 inline Tick cycles(int numCycles) const { return clock * numCycles; }
58 inline Tick curCycle() const { return curTick / clock; }
59
60#if FULL_SYSTEM
61 protected:
62 uint64_t interrupts[TheISA::NumInterruptLevels];
63 uint64_t intstatus;
64
65 public:
66 virtual void post_interrupt(int int_num, int index);
67 virtual void clear_interrupt(int int_num, int index);
68 virtual void clear_interrupts();
69 bool checkInterrupts;
70
71 bool check_interrupt(int int_num) const {
72 if (int_num > TheISA::NumInterruptLevels)
73 panic("int_num out of bounds\n");
74
75 return interrupts[int_num] != 0;
76 }
77
78 bool check_interrupts() const { return intstatus != 0; }
79 uint64_t intr_status() const { return intstatus; }
80
81 class ProfileEvent : public Event
82 {
83 private:
84 BaseCPU *cpu;
85 int interval;
86
87 public:
88 ProfileEvent(BaseCPU *cpu, int interval);
89 void process();
90 };
91 ProfileEvent *profileEvent;
92#endif
93
94 protected:
95 std::vector<ThreadContext *> threadContexts;
96
97 public:
98
99 /// Notify the CPU that the indicated context is now active. The
100 /// delay parameter indicates the number of ticks to wait before
101 /// executing (typically 0 or 1).
102 virtual void activateContext(int thread_num, int delay) {}
103
104 /// Notify the CPU that the indicated context is now suspended.
105 virtual void suspendContext(int thread_num) {}
106
107 /// Notify the CPU that the indicated context is now deallocated.
108 virtual void deallocateContext(int thread_num) {}
109
110 /// Notify the CPU that the indicated context is now halted.
111 virtual void haltContext(int thread_num) {}
112
113 public:
114 struct Params
115 {
116 std::string name;
117 int numberOfThreads;
118 bool deferRegistration;
119 Counter max_insts_any_thread;
120 Counter max_insts_all_threads;
121 Counter max_loads_any_thread;
122 Counter max_loads_all_threads;
| 74 inline Tick frequency() const { return Clock::Frequency / clock; }
75 inline Tick cycles(int numCycles) const { return clock * numCycles; }
76 inline Tick curCycle() const { return curTick / clock; }
77
78#if FULL_SYSTEM
79 protected:
80 uint64_t interrupts[TheISA::NumInterruptLevels];
81 uint64_t intstatus;
82
83 public:
84 virtual void post_interrupt(int int_num, int index);
85 virtual void clear_interrupt(int int_num, int index);
86 virtual void clear_interrupts();
87 bool checkInterrupts;
88
89 bool check_interrupt(int int_num) const {
90 if (int_num > TheISA::NumInterruptLevels)
91 panic("int_num out of bounds\n");
92
93 return interrupts[int_num] != 0;
94 }
95
96 bool check_interrupts() const { return intstatus != 0; }
97 uint64_t intr_status() const { return intstatus; }
98
99 class ProfileEvent : public Event
100 {
101 private:
102 BaseCPU *cpu;
103 int interval;
104
105 public:
106 ProfileEvent(BaseCPU *cpu, int interval);
107 void process();
108 };
109 ProfileEvent *profileEvent;
110#endif
111
112 protected:
113 std::vector<ThreadContext *> threadContexts;
114
115 public:
116
117 /// Notify the CPU that the indicated context is now active. The
118 /// delay parameter indicates the number of ticks to wait before
119 /// executing (typically 0 or 1).
120 virtual void activateContext(int thread_num, int delay) {}
121
122 /// Notify the CPU that the indicated context is now suspended.
123 virtual void suspendContext(int thread_num) {}
124
125 /// Notify the CPU that the indicated context is now deallocated.
126 virtual void deallocateContext(int thread_num) {}
127
128 /// Notify the CPU that the indicated context is now halted.
129 virtual void haltContext(int thread_num) {}
130
131 public:
132 struct Params
133 {
134 std::string name;
135 int numberOfThreads;
136 bool deferRegistration;
137 Counter max_insts_any_thread;
138 Counter max_insts_all_threads;
139 Counter max_loads_any_thread;
140 Counter max_loads_all_threads;
|
| 141 Counter stats_reset_inst;
|
123 Tick clock;
124 bool functionTrace;
125 Tick functionTraceStart;
126 System *system;
127#if FULL_SYSTEM
128 int cpu_id;
129 Tick profile;
130#endif
| 142 Tick clock;
143 bool functionTrace;
144 Tick functionTraceStart;
145 System *system;
146#if FULL_SYSTEM
147 int cpu_id;
148 Tick profile;
149#endif
|
| 150 Tick progress_interval;
|
131 BaseCPU *checker;
132
133 Params();
134 };
135
136 const Params *params;
137
138 BaseCPU(Params *params);
139 virtual ~BaseCPU();
140
141 virtual void init();
142 virtual void startup();
143 virtual void regStats();
144
145 virtual void activateWhenReady(int tid) {};
146
147 void registerThreadContexts();
148
149 /// Prepare for another CPU to take over execution. When it is
150 /// is ready (drained pipe) it signals the sampler.
151 virtual void switchOut();
152
153 /// Take over execution from the given CPU. Used for warm-up and
154 /// sampling.
155 virtual void takeOverFrom(BaseCPU *);
156
157 /**
158 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
159 * This is a constant for the duration of the simulation.
160 */
161 int number_of_threads;
162
163 /**
164 * Vector of per-thread instruction-based event queues. Used for
165 * scheduling events based on number of instructions committed by
166 * a particular thread.
167 */
168 EventQueue **comInstEventQueue;
169
170 /**
171 * Vector of per-thread load-based event queues. Used for
172 * scheduling events based on number of loads committed by
173 *a particular thread.
174 */
175 EventQueue **comLoadEventQueue;
176
177 System *system;
178
179#if FULL_SYSTEM
180 /**
181 * Serialize this object to the given output stream.
182 * @param os The stream to serialize to.
183 */
184 virtual void serialize(std::ostream &os);
185
186 /**
187 * Reconstruct the state of this object from a checkpoint.
188 * @param cp The checkpoint use.
189 * @param section The section name of this object
190 */
191 virtual void unserialize(Checkpoint *cp, const std::string §ion);
192
193#endif
194
195 /**
196 * Return pointer to CPU's branch predictor (NULL if none).
197 * @return Branch predictor pointer.
198 */
199 virtual BranchPred *getBranchPred() { return NULL; };
200
201 virtual Counter totalInstructions() const { return 0; }
202
203 // Function tracing
204 private:
205 bool functionTracingEnabled;
206 std::ostream *functionTraceStream;
207 Addr currentFunctionStart;
208 Addr currentFunctionEnd;
209 Tick functionEntryTick;
210 void enableFunctionTrace();
211 void traceFunctionsInternal(Addr pc);
212
213 protected:
214 void traceFunctions(Addr pc)
215 {
216 if (functionTracingEnabled)
217 traceFunctionsInternal(pc);
218 }
219
220 private:
221 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
222
223 public:
224 static int numSimulatedCPUs() { return cpuList.size(); }
225 static Counter numSimulatedInstructions()
226 {
227 Counter total = 0;
228
229 int size = cpuList.size();
230 for (int i = 0; i < size; ++i)
231 total += cpuList[i]->totalInstructions();
232
233 return total;
234 }
235
236 public:
237 // Number of CPU cycles simulated
238 Stats::Scalar<> numCycles;
239};
240
241#endif // __CPU_BASE_HH__
| 151 BaseCPU *checker;
152
153 Params();
154 };
155
156 const Params *params;
157
158 BaseCPU(Params *params);
159 virtual ~BaseCPU();
160
161 virtual void init();
162 virtual void startup();
163 virtual void regStats();
164
165 virtual void activateWhenReady(int tid) {};
166
167 void registerThreadContexts();
168
169 /// Prepare for another CPU to take over execution. When it is
170 /// is ready (drained pipe) it signals the sampler.
171 virtual void switchOut();
172
173 /// Take over execution from the given CPU. Used for warm-up and
174 /// sampling.
175 virtual void takeOverFrom(BaseCPU *);
176
177 /**
178 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
179 * This is a constant for the duration of the simulation.
180 */
181 int number_of_threads;
182
183 /**
184 * Vector of per-thread instruction-based event queues. Used for
185 * scheduling events based on number of instructions committed by
186 * a particular thread.
187 */
188 EventQueue **comInstEventQueue;
189
190 /**
191 * Vector of per-thread load-based event queues. Used for
192 * scheduling events based on number of loads committed by
193 *a particular thread.
194 */
195 EventQueue **comLoadEventQueue;
196
197 System *system;
198
199#if FULL_SYSTEM
200 /**
201 * Serialize this object to the given output stream.
202 * @param os The stream to serialize to.
203 */
204 virtual void serialize(std::ostream &os);
205
206 /**
207 * Reconstruct the state of this object from a checkpoint.
208 * @param cp The checkpoint use.
209 * @param section The section name of this object
210 */
211 virtual void unserialize(Checkpoint *cp, const std::string §ion);
212
213#endif
214
215 /**
216 * Return pointer to CPU's branch predictor (NULL if none).
217 * @return Branch predictor pointer.
218 */
219 virtual BranchPred *getBranchPred() { return NULL; };
220
221 virtual Counter totalInstructions() const { return 0; }
222
223 // Function tracing
224 private:
225 bool functionTracingEnabled;
226 std::ostream *functionTraceStream;
227 Addr currentFunctionStart;
228 Addr currentFunctionEnd;
229 Tick functionEntryTick;
230 void enableFunctionTrace();
231 void traceFunctionsInternal(Addr pc);
232
233 protected:
234 void traceFunctions(Addr pc)
235 {
236 if (functionTracingEnabled)
237 traceFunctionsInternal(pc);
238 }
239
240 private:
241 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
242
243 public:
244 static int numSimulatedCPUs() { return cpuList.size(); }
245 static Counter numSimulatedInstructions()
246 {
247 Counter total = 0;
248
249 int size = cpuList.size();
250 for (int i = 0; i < size; ++i)
251 total += cpuList[i]->totalInstructions();
252
253 return total;
254 }
255
256 public:
257 // Number of CPU cycles simulated
258 Stats::Scalar<> numCycles;
259};
260
261#endif // __CPU_BASE_HH__
|