1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert
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27 */ 28 29#ifndef __CPU_BASE_HH__ 30#define __CPU_BASE_HH__ 31 32#include <vector> 33 34#include "base/statistics.hh" 35#include "config/full_system.hh" 36#include "cpu/sampler/sampler.hh" 37#include "sim/eventq.hh" 38#include "sim/sim_object.hh" 39#include "arch/isa_traits.hh" 40
| 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "cpu/sampler/sampler.hh" 40#include "sim/eventq.hh" 41#include "sim/sim_object.hh" 42#include "arch/isa_traits.hh" 43
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| 44class System; 45namespace Kernel { class Statistics; }
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41class BranchPred;
| 46class BranchPred;
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42class CheckerCPU;
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43class ExecContext;
| 47class ExecContext;
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44class System;
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45 46class BaseCPU : public SimObject 47{ 48 protected: 49 // CPU's clock period in terms of the number of ticks of curTime. 50 Tick clock; 51 52 public: 53 inline Tick frequency() const { return Clock::Frequency / clock; } 54 inline Tick cycles(int numCycles) const { return clock * numCycles; } 55 inline Tick curCycle() const { return curTick / clock; } 56 57#if FULL_SYSTEM 58 protected: 59 uint64_t interrupts[TheISA::NumInterruptLevels]; 60 uint64_t intstatus; 61 62 public: 63 virtual void post_interrupt(int int_num, int index); 64 virtual void clear_interrupt(int int_num, int index); 65 virtual void clear_interrupts(); 66 bool checkInterrupts; 67 68 bool check_interrupt(int int_num) const { 69 if (int_num > TheISA::NumInterruptLevels) 70 panic("int_num out of bounds\n"); 71 72 return interrupts[int_num] != 0; 73 } 74 75 bool check_interrupts() const { return intstatus != 0; } 76 uint64_t intr_status() const { return intstatus; } 77 78 class ProfileEvent : public Event 79 { 80 private: 81 BaseCPU *cpu; 82 int interval; 83 84 public: 85 ProfileEvent(BaseCPU *cpu, int interval); 86 void process(); 87 }; 88 ProfileEvent *profileEvent; 89#endif 90 91 protected: 92 std::vector<ExecContext *> execContexts; 93 94 public: 95 96 /// Notify the CPU that the indicated context is now active. The 97 /// delay parameter indicates the number of ticks to wait before 98 /// executing (typically 0 or 1). 99 virtual void activateContext(int thread_num, int delay) {} 100 101 /// Notify the CPU that the indicated context is now suspended. 102 virtual void suspendContext(int thread_num) {} 103 104 /// Notify the CPU that the indicated context is now deallocated. 105 virtual void deallocateContext(int thread_num) {} 106 107 /// Notify the CPU that the indicated context is now halted. 108 virtual void haltContext(int thread_num) {} 109 110 public: 111 struct Params 112 { 113 std::string name; 114 int numberOfThreads; 115 bool deferRegistration; 116 Counter max_insts_any_thread; 117 Counter max_insts_all_threads; 118 Counter max_loads_any_thread; 119 Counter max_loads_all_threads; 120 Tick clock; 121 bool functionTrace; 122 Tick functionTraceStart; 123 System *system; 124#if FULL_SYSTEM 125 int cpu_id; 126 Tick profile; 127#endif
| 48 49class BaseCPU : public SimObject 50{ 51 protected: 52 // CPU's clock period in terms of the number of ticks of curTime. 53 Tick clock; 54 55 public: 56 inline Tick frequency() const { return Clock::Frequency / clock; } 57 inline Tick cycles(int numCycles) const { return clock * numCycles; } 58 inline Tick curCycle() const { return curTick / clock; } 59 60#if FULL_SYSTEM 61 protected: 62 uint64_t interrupts[TheISA::NumInterruptLevels]; 63 uint64_t intstatus; 64 65 public: 66 virtual void post_interrupt(int int_num, int index); 67 virtual void clear_interrupt(int int_num, int index); 68 virtual void clear_interrupts(); 69 bool checkInterrupts; 70 71 bool check_interrupt(int int_num) const { 72 if (int_num > TheISA::NumInterruptLevels) 73 panic("int_num out of bounds\n"); 74 75 return interrupts[int_num] != 0; 76 } 77 78 bool check_interrupts() const { return intstatus != 0; } 79 uint64_t intr_status() const { return intstatus; } 80 81 class ProfileEvent : public Event 82 { 83 private: 84 BaseCPU *cpu; 85 int interval; 86 87 public: 88 ProfileEvent(BaseCPU *cpu, int interval); 89 void process(); 90 }; 91 ProfileEvent *profileEvent; 92#endif 93 94 protected: 95 std::vector<ExecContext *> execContexts; 96 97 public: 98 99 /// Notify the CPU that the indicated context is now active. The 100 /// delay parameter indicates the number of ticks to wait before 101 /// executing (typically 0 or 1). 102 virtual void activateContext(int thread_num, int delay) {} 103 104 /// Notify the CPU that the indicated context is now suspended. 105 virtual void suspendContext(int thread_num) {} 106 107 /// Notify the CPU that the indicated context is now deallocated. 108 virtual void deallocateContext(int thread_num) {} 109 110 /// Notify the CPU that the indicated context is now halted. 111 virtual void haltContext(int thread_num) {} 112 113 public: 114 struct Params 115 { 116 std::string name; 117 int numberOfThreads; 118 bool deferRegistration; 119 Counter max_insts_any_thread; 120 Counter max_insts_all_threads; 121 Counter max_loads_any_thread; 122 Counter max_loads_all_threads; 123 Tick clock; 124 bool functionTrace; 125 Tick functionTraceStart; 126 System *system; 127#if FULL_SYSTEM 128 int cpu_id; 129 Tick profile; 130#endif
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128 BaseCPU *checker;
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129 130 Params(); 131 }; 132 133 const Params *params; 134 135 BaseCPU(Params *params); 136 virtual ~BaseCPU(); 137 138 virtual void init(); 139 virtual void startup(); 140 virtual void regStats(); 141 142 virtual void activateWhenReady(int tid) {}; 143 144 void registerExecContexts(); 145 146 /// Prepare for another CPU to take over execution. When it is 147 /// is ready (drained pipe) it signals the sampler. 148 virtual void switchOut(Sampler *); 149 150 /// Take over execution from the given CPU. Used for warm-up and 151 /// sampling. 152 virtual void takeOverFrom(BaseCPU *); 153 154 /** 155 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 156 * This is a constant for the duration of the simulation. 157 */ 158 int number_of_threads; 159 160 /** 161 * Vector of per-thread instruction-based event queues. Used for 162 * scheduling events based on number of instructions committed by 163 * a particular thread. 164 */ 165 EventQueue **comInstEventQueue; 166 167 /** 168 * Vector of per-thread load-based event queues. Used for 169 * scheduling events based on number of loads committed by 170 *a particular thread. 171 */ 172 EventQueue **comLoadEventQueue; 173 174 System *system; 175 176#if FULL_SYSTEM 177 /** 178 * Serialize this object to the given output stream. 179 * @param os The stream to serialize to. 180 */ 181 virtual void serialize(std::ostream &os); 182 183 /** 184 * Reconstruct the state of this object from a checkpoint. 185 * @param cp The checkpoint use. 186 * @param section The section name of this object 187 */ 188 virtual void unserialize(Checkpoint *cp, const std::string §ion); 189 190#endif 191 192 /** 193 * Return pointer to CPU's branch predictor (NULL if none). 194 * @return Branch predictor pointer. 195 */ 196 virtual BranchPred *getBranchPred() { return NULL; }; 197 198 virtual Counter totalInstructions() const { return 0; } 199 200 // Function tracing 201 private: 202 bool functionTracingEnabled; 203 std::ostream *functionTraceStream; 204 Addr currentFunctionStart; 205 Addr currentFunctionEnd; 206 Tick functionEntryTick; 207 void enableFunctionTrace(); 208 void traceFunctionsInternal(Addr pc); 209 210 protected: 211 void traceFunctions(Addr pc) 212 { 213 if (functionTracingEnabled) 214 traceFunctionsInternal(pc); 215 } 216 217 private: 218 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 219 220 public: 221 static int numSimulatedCPUs() { return cpuList.size(); } 222 static Counter numSimulatedInstructions() 223 { 224 Counter total = 0; 225 226 int size = cpuList.size(); 227 for (int i = 0; i < size; ++i) 228 total += cpuList[i]->totalInstructions(); 229 230 return total; 231 } 232 233 public: 234 // Number of CPU cycles simulated 235 Stats::Scalar<> numCycles;
| 131 132 Params(); 133 }; 134 135 const Params *params; 136 137 BaseCPU(Params *params); 138 virtual ~BaseCPU(); 139 140 virtual void init(); 141 virtual void startup(); 142 virtual void regStats(); 143 144 virtual void activateWhenReady(int tid) {}; 145 146 void registerExecContexts(); 147 148 /// Prepare for another CPU to take over execution. When it is 149 /// is ready (drained pipe) it signals the sampler. 150 virtual void switchOut(Sampler *); 151 152 /// Take over execution from the given CPU. Used for warm-up and 153 /// sampling. 154 virtual void takeOverFrom(BaseCPU *); 155 156 /** 157 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 158 * This is a constant for the duration of the simulation. 159 */ 160 int number_of_threads; 161 162 /** 163 * Vector of per-thread instruction-based event queues. Used for 164 * scheduling events based on number of instructions committed by 165 * a particular thread. 166 */ 167 EventQueue **comInstEventQueue; 168 169 /** 170 * Vector of per-thread load-based event queues. Used for 171 * scheduling events based on number of loads committed by 172 *a particular thread. 173 */ 174 EventQueue **comLoadEventQueue; 175 176 System *system; 177 178#if FULL_SYSTEM 179 /** 180 * Serialize this object to the given output stream. 181 * @param os The stream to serialize to. 182 */ 183 virtual void serialize(std::ostream &os); 184 185 /** 186 * Reconstruct the state of this object from a checkpoint. 187 * @param cp The checkpoint use. 188 * @param section The section name of this object 189 */ 190 virtual void unserialize(Checkpoint *cp, const std::string §ion); 191 192#endif 193 194 /** 195 * Return pointer to CPU's branch predictor (NULL if none). 196 * @return Branch predictor pointer. 197 */ 198 virtual BranchPred *getBranchPred() { return NULL; }; 199 200 virtual Counter totalInstructions() const { return 0; } 201 202 // Function tracing 203 private: 204 bool functionTracingEnabled; 205 std::ostream *functionTraceStream; 206 Addr currentFunctionStart; 207 Addr currentFunctionEnd; 208 Tick functionEntryTick; 209 void enableFunctionTrace(); 210 void traceFunctionsInternal(Addr pc); 211 212 protected: 213 void traceFunctions(Addr pc) 214 { 215 if (functionTracingEnabled) 216 traceFunctionsInternal(pc); 217 } 218 219 private: 220 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 221 222 public: 223 static int numSimulatedCPUs() { return cpuList.size(); } 224 static Counter numSimulatedInstructions() 225 { 226 Counter total = 0; 227 228 int size = cpuList.size(); 229 for (int i = 0; i < size; ++i) 230 total += cpuList[i]->totalInstructions(); 231 232 return total; 233 } 234 235 public: 236 // Number of CPU cycles simulated 237 Stats::Scalar<> numCycles;
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| 238 239#if FULL_SYSTEM 240 Kernel::Statistics *kernelStats; 241#endif
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236}; 237 238#endif // __CPU_BASE_HH__
| 242}; 243 244#endif // __CPU_BASE_HH__
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