base.hh (9332:ae2a5329ce96) | base.hh (9430:a113f27b68bd) |
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1/* | 1/* |
2 * Copyright (c) 2011 ARM Limited | 2 * Copyright (c) 2011-2012 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 98 unchanged lines hidden (view full) --- 109 * can track which process IDs are ultimately interacting with them 110 */ 111 uint32_t _taskId; 112 113 /** The current OS process ID that is executing on this processor. This is 114 * used to generate a taskId */ 115 uint32_t _pid; 116 | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 98 unchanged lines hidden (view full) --- 109 * can track which process IDs are ultimately interacting with them 110 */ 111 uint32_t _taskId; 112 113 /** The current OS process ID that is executing on this processor. This is 114 * used to generate a taskId */ 115 uint32_t _pid; 116 |
117 /** Is the CPU switched out or active? */ 118 bool _switchedOut; 119 |
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117 /** 118 * Define a base class for the CPU ports (instruction and data) 119 * that is refined in the subclasses. This class handles the 120 * common cases, i.e. the functional accesses and the status 121 * changes and address range queries. The default behaviour for 122 * both atomic and timing access is to panic and the corresponding 123 * subclasses have to override these methods. 124 */ --- 191 unchanged lines hidden (view full) --- 316 * are already connected) to the memories connected to the old 317 * CPU. 318 * 319 * @param cpu CPU to initialize read state from. 320 */ 321 virtual void takeOverFrom(BaseCPU *cpu); 322 323 /** | 120 /** 121 * Define a base class for the CPU ports (instruction and data) 122 * that is refined in the subclasses. This class handles the 123 * common cases, i.e. the functional accesses and the status 124 * changes and address range queries. The default behaviour for 125 * both atomic and timing access is to panic and the corresponding 126 * subclasses have to override these methods. 127 */ --- 191 unchanged lines hidden (view full) --- 319 * are already connected) to the memories connected to the old 320 * CPU. 321 * 322 * @param cpu CPU to initialize read state from. 323 */ 324 virtual void takeOverFrom(BaseCPU *cpu); 325 326 /** |
327 * Determine if the CPU is switched out. 328 * 329 * @return True if the CPU is switched out, false otherwise. 330 */ 331 bool switchedOut() const { return _switchedOut; } 332 333 /** |
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324 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 325 * This is a constant for the duration of the simulation. 326 */ 327 ThreadID numThreads; 328 329 /** 330 * Vector of per-thread instruction-based event queues. Used for 331 * scheduling events based on number of instructions committed by --- 87 unchanged lines hidden --- | 334 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 335 * This is a constant for the duration of the simulation. 336 */ 337 ThreadID numThreads; 338 339 /** 340 * Vector of per-thread instruction-based event queues. Used for 341 * scheduling events based on number of instructions committed by --- 87 unchanged lines hidden --- |