base.hh (8922:17f037ad8918) | base.hh (8926:570b44fe6e04) |
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1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 156 unchanged lines hidden (view full) --- 165 int cpuId() { return _cpuId; } 166 167 /** Reads this CPU's unique data requestor ID */ 168 MasterID dataMasterId() { return _dataMasterId; } 169 /** Reads this CPU's unique instruction requestor ID */ 170 MasterID instMasterId() { return _instMasterId; } 171 172 /** | 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 156 unchanged lines hidden (view full) --- 165 int cpuId() { return _cpuId; } 166 167 /** Reads this CPU's unique data requestor ID */ 168 MasterID dataMasterId() { return _dataMasterId; } 169 /** Reads this CPU's unique instruction requestor ID */ 170 MasterID instMasterId() { return _instMasterId; } 171 172 /** |
173 * Get a master port on this MemObject. This method is virtual to allow 174 * the subclasses of the BaseCPU to override it. All CPUs have a 175 * data and instruction port, but the Atomic CPU (in its current 176 * form) adds a port directly connected to the memory and has to 177 * override getMasterPort. | 173 * Get a master port on this CPU. All CPUs have a data and 174 * instruction port, and this method uses getDataPort and 175 * getInstPort of the subclasses to resolve the two ports. |
178 * | 176 * |
179 * This method uses getDataPort and getInstPort to resolve the two 180 * ports. 181 * | |
182 * @param if_name the port name 183 * @param idx ignored index 184 * 185 * @return a reference to the port with the given name 186 */ | 177 * @param if_name the port name 178 * @param idx ignored index 179 * 180 * @return a reference to the port with the given name 181 */ |
187 virtual MasterPort &getMasterPort(const std::string &if_name, 188 int idx = -1); | 182 MasterPort &getMasterPort(const std::string &if_name, int idx = -1); |
189 190// Tick currentTick; 191 inline Tick frequency() const { return SimClock::Frequency / clock; } 192 inline Tick ticks(int numCycles) const { return clock * numCycles; } 193 inline Tick curCycle() const { return curTick() / clock; } 194 inline Tick tickToCycles(Tick val) const { return val / clock; } 195 inline void workItemBegin() { numWorkItemsStarted++; } 196 inline void workItemEnd() { numWorkItemsCompleted++; } --- 224 unchanged lines hidden --- | 183 184// Tick currentTick; 185 inline Tick frequency() const { return SimClock::Frequency / clock; } 186 inline Tick ticks(int numCycles) const { return clock * numCycles; } 187 inline Tick curCycle() const { return curTick() / clock; } 188 inline Tick tickToCycles(Tick val) const { return val / clock; } 189 inline void workItemBegin() { numWorkItemsStarted++; } 190 inline void workItemEnd() { numWorkItemsCompleted++; } --- 224 unchanged lines hidden --- |