1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#ifndef __CPU_BASE_HH__
47#define __CPU_BASE_HH__
48
49#include <vector>
50
51#include "arch/interrupts.hh"
52#include "arch/isa_traits.hh"
53#include "arch/microcode_rom.hh"
54#include "base/statistics.hh"
55#include "config/the_isa.hh"
56#include "mem/mem_object.hh"
57#include "sim/eventq.hh"
58#include "sim/full_system.hh"
59#include "sim/insttracer.hh"
60
61class BaseCPUParams;
62class BranchPred;
63class CheckerCPU;
64class ThreadContext;
65class System;
66class Port;
67
68namespace TheISA
69{
70 class Predecoder;
71}
72
73class CPUProgressEvent : public Event
74{
75 protected:
76 Tick _interval;
77 Counter lastNumInst;
78 BaseCPU *cpu;
79 bool _repeatEvent;
80
81 public:
82 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
83
84 void process();
85
86 void interval(Tick ival) { _interval = ival; }
87 Tick interval() { return _interval; }
88
89 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
90
91 virtual const char *description() const;
92};
93
94class BaseCPU : public MemObject
95{
96 protected:
97 // CPU's clock period in terms of the number of ticks of curTime.
98 Tick clock;
99 // @todo remove me after debugging with legion done
100 Tick instCnt;
101 // every cpu has an id, put it in the base cpu
102 // Set at initialization, only time a cpuId might change is during a
103 // takeover (which should be done from within the BaseCPU anyway,
104 // therefore no setCpuId() method is provided
105 int _cpuId;
106
107 /**
108 * Define a base class for the CPU ports (instruction and data)
109 * that is refined in the subclasses. This class handles the
110 * common cases, i.e. the functional accesses and the status
111 * changes and address range queries. The default behaviour for
112 * both atomic and timing access is to panic and the corresponding
113 * subclasses have to override these methods.
114 */
115 class CpuPort : public Port
116 {
117 public:
118
119 /**
120 * Create a CPU port with a name and a structural owner.
121 *
122 * @param _name port name including the owner
123 * @param _name structural owner of this port
124 */
125 CpuPort(const std::string& _name, MemObject* _owner) :
126 Port(_name, _owner)
127 { }
128
129 protected:
130
131 virtual bool recvTiming(PacketPtr pkt);
132
133 virtual Tick recvAtomic(PacketPtr pkt);
134
135 virtual void recvRetry();
136
137 void recvFunctional(PacketPtr pkt);
138
139 void recvRangeChange();
140
141 };
142
143 public:
144 /** Reads this CPU's ID. */
145 int cpuId() { return _cpuId; }
146
147// Tick currentTick;
148 inline Tick frequency() const { return SimClock::Frequency / clock; }
149 inline Tick ticks(int numCycles) const { return clock * numCycles; }
150 inline Tick curCycle() const { return curTick() / clock; }
151 inline Tick tickToCycles(Tick val) const { return val / clock; }
152 inline void workItemBegin() { numWorkItemsStarted++; }
153 inline void workItemEnd() { numWorkItemsCompleted++; }
154 // @todo remove me after debugging with legion done
155 Tick instCount() { return instCnt; }
156
157 /** The next cycle the CPU should be scheduled, given a cache
158 * access or quiesce event returning on this cycle. This function
159 * may return curTick() if the CPU should run on the current cycle.
160 */
161 Tick nextCycle();
162
163 /** The next cycle the CPU should be scheduled, given a cache
164 * access or quiesce event returning on the given Tick. This
165 * function may return curTick() if the CPU should run on the
166 * current cycle.
167 * @param begin_tick The tick that the event is completing on.
168 */
169 Tick nextCycle(Tick begin_tick);
170
171 TheISA::MicrocodeRom microcodeRom;
172
173 protected:
174 TheISA::Interrupts *interrupts;
175
176 public:
177 TheISA::Interrupts *
178 getInterruptController()
179 {
180 return interrupts;
181 }
182
183 virtual void wakeup() = 0;
184
185 void
186 postInterrupt(int int_num, int index)
187 {
188 interrupts->post(int_num, index);
189 if (FullSystem)
190 wakeup();
191 }
192
193 void
194 clearInterrupt(int int_num, int index)
195 {
196 interrupts->clear(int_num, index);
197 }
198
199 void
200 clearInterrupts()
201 {
202 interrupts->clearAll();
203 }
204
205 bool
206 checkInterrupts(ThreadContext *tc) const
207 {
208 return FullSystem && interrupts->checkInterrupts(tc);
209 }
210
211 class ProfileEvent : public Event
212 {
213 private:
214 BaseCPU *cpu;
215 Tick interval;
216
217 public:
218 ProfileEvent(BaseCPU *cpu, Tick interval);
219 void process();
220 };
221 ProfileEvent *profileEvent;
222
223 protected:
224 std::vector<ThreadContext *> threadContexts;
225 std::vector<TheISA::Predecoder *> predecoders;
226
227 Trace::InstTracer * tracer;
228
229 public:
230
231 // Mask to align PCs to MachInst sized boundaries
232 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
233
234 /// Provide access to the tracer pointer
235 Trace::InstTracer * getTracer() { return tracer; }
236
237 /// Notify the CPU that the indicated context is now active. The
238 /// delay parameter indicates the number of ticks to wait before
239 /// executing (typically 0 or 1).
240 virtual void activateContext(ThreadID thread_num, int delay) {}
241
242 /// Notify the CPU that the indicated context is now suspended.
243 virtual void suspendContext(ThreadID thread_num) {}
244
245 /// Notify the CPU that the indicated context is now deallocated.
246 virtual void deallocateContext(ThreadID thread_num) {}
247
248 /// Notify the CPU that the indicated context is now halted.
249 virtual void haltContext(ThreadID thread_num) {}
250
251 /// Given a Thread Context pointer return the thread num
252 int findContext(ThreadContext *tc);
253
254 /// Given a thread num get tho thread context for it
255 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
256
257 public:
258 typedef BaseCPUParams Params;
259 const Params *params() const
260 { return reinterpret_cast<const Params *>(_params); }
261 BaseCPU(Params *params);
262 virtual ~BaseCPU();
263
264 virtual void init();
265 virtual void startup();
266 virtual void regStats();
267
268 virtual void activateWhenReady(ThreadID tid) {};
269
270 void registerThreadContexts();
271
272 /// Prepare for another CPU to take over execution. When it is
273 /// is ready (drained pipe) it signals the sampler.
274 virtual void switchOut();
275
276 /// Take over execution from the given CPU. Used for warm-up and
277 /// sampling.
278 virtual void takeOverFrom(BaseCPU *);
279
280 /**
281 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
282 * This is a constant for the duration of the simulation.
283 */
284 ThreadID numThreads;
285
286 /**
287 * Vector of per-thread instruction-based event queues. Used for
288 * scheduling events based on number of instructions committed by
289 * a particular thread.
290 */
291 EventQueue **comInstEventQueue;
292
293 /**
294 * Vector of per-thread load-based event queues. Used for
295 * scheduling events based on number of loads committed by
296 *a particular thread.
297 */
298 EventQueue **comLoadEventQueue;
299
300 System *system;
301
302 Tick phase;
303
304 /**
305 * Serialize this object to the given output stream.
306 * @param os The stream to serialize to.
307 */
308 virtual void serialize(std::ostream &os);
309
310 /**
311 * Reconstruct the state of this object from a checkpoint.
312 * @param cp The checkpoint use.
313 * @param section The section name of this object
314 */
315 virtual void unserialize(Checkpoint *cp, const std::string &section);
316
317 /**
318 * Return pointer to CPU's branch predictor (NULL if none).
319 * @return Branch predictor pointer.
320 */
321 virtual BranchPred *getBranchPred() { return NULL; };
322
323 virtual Counter totalInstructions() const = 0;
324
325 // Function tracing
326 private:
327 bool functionTracingEnabled;
328 std::ostream *functionTraceStream;
329 Addr currentFunctionStart;
330 Addr currentFunctionEnd;
331 Tick functionEntryTick;
332 void enableFunctionTrace();
333 void traceFunctionsInternal(Addr pc);
334
335 private:
336 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
337
338 public:
339 void traceFunctions(Addr pc)
340 {
341 if (functionTracingEnabled)
342 traceFunctionsInternal(pc);
343 }
344
345 static int numSimulatedCPUs() { return cpuList.size(); }
346 static Counter numSimulatedInstructions()
347 {
348 Counter total = 0;
349
350 int size = cpuList.size();
351 for (int i = 0; i < size; ++i)
352 total += cpuList[i]->totalInstructions();
353
354 return total;
355 }
356
357 public:
358 // Number of CPU cycles simulated
359 Stats::Scalar numCycles;
360 Stats::Scalar numWorkItemsStarted;
361 Stats::Scalar numWorkItemsCompleted;
362};
363
364#endif // __CPU_BASE_HH__