1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "sim/eventq.hh"
40#include "mem/mem_object.hh"
41#include "arch/isa_traits.hh"
42
43#if FULL_SYSTEM
44#include "arch/interrupts.hh"
45#endif
46
47class BranchPred;
48class CheckerCPU;
49class ThreadContext;
50class System;
51class Port;
52
53class CPUProgressEvent : public Event
54{
55 protected:
56 Tick interval;
57 Counter lastNumInst;
58 BaseCPU *cpu;
59
60 public:
61 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
62
63 void process();
64
65 virtual const char *description();
66};
67
68class BaseCPU : public MemObject
69{
70 protected:
71 // CPU's clock period in terms of the number of ticks of curTime.
72 Tick clock;
73
74 public:
75// Tick currentTick;
76 inline Tick frequency() const { return Clock::Frequency / clock; }
77 inline Tick cycles(int numCycles) const { return clock * numCycles; }
78 inline Tick curCycle() const { return curTick / clock; }
79
80 /** The next cycle the CPU should be scheduled, given a cache
81 * access or quiesce event returning on this cycle. This function
82 * may return curTick if the CPU should run on the current cycle.
83 */
84 Tick nextCycle();
85
86 /** The next cycle the CPU should be scheduled, given a cache
87 * access or quiesce event returning on the given Tick. This
88 * function may return curTick if the CPU should run on the
89 * current cycle.
90 * @param begin_tick The tick that the event is completing on.
91 */
92 Tick nextCycle(Tick begin_tick);
93
94#if FULL_SYSTEM
95 protected:
96// uint64_t interrupts[TheISA::NumInterruptLevels];
97// uint64_t intstatus;
98 TheISA::Interrupts interrupts;
99
100 public:
101 virtual void post_interrupt(int int_num, int index);
102 virtual void clear_interrupt(int int_num, int index);
103 virtual void clear_interrupts();
104 bool checkInterrupts;
105
106 bool check_interrupts(ThreadContext * tc) const
107 { return interrupts.check_interrupts(tc); }
108
109 class ProfileEvent : public Event
110 {
111 private:
112 BaseCPU *cpu;
113 int interval;
114
115 public:
116 ProfileEvent(BaseCPU *cpu, int interval);
117 void process();
118 };
119 ProfileEvent *profileEvent;
120#endif
121
122 protected:
123 std::vector<ThreadContext *> threadContexts;
124
125 public:
126
127 /// Notify the CPU that the indicated context is now active. The
128 /// delay parameter indicates the number of ticks to wait before
129 /// executing (typically 0 or 1).
130 virtual void activateContext(int thread_num, int delay) {}
131
132 /// Notify the CPU that the indicated context is now suspended.
133 virtual void suspendContext(int thread_num) {}
134
135 /// Notify the CPU that the indicated context is now deallocated.
136 virtual void deallocateContext(int thread_num) {}
137
138 /// Notify the CPU that the indicated context is now halted.
139 virtual void haltContext(int thread_num) {}
140
141 public:
142 struct Params
143 {
144 std::string name;
145 int numberOfThreads;
146 bool deferRegistration;
147 Counter max_insts_any_thread;
148 Counter max_insts_all_threads;
149 Counter max_loads_any_thread;
150 Counter max_loads_all_threads;
151 Tick clock;
152 bool functionTrace;
153 Tick functionTraceStart;
154 System *system;
155 int cpu_id;
156 Tick phase;
157#if FULL_SYSTEM
158 Tick profile;
159
160 bool do_statistics_insts;
161 bool do_checkpoint_insts;
162 bool do_quiesce;
163#endif
164 Tick progress_interval;
165 BaseCPU *checker;
166
167 Params();
168 };
169
170 const Params *params;
171
172 BaseCPU(Params *params);
173 virtual ~BaseCPU();
174
175 virtual void init();
176 virtual void startup();
177 virtual void regStats();
178
179 virtual void activateWhenReady(int tid) {};
180
181 void registerThreadContexts();
182
183 /// Prepare for another CPU to take over execution. When it is
184 /// is ready (drained pipe) it signals the sampler.
185 virtual void switchOut();
186
187 /// Take over execution from the given CPU. Used for warm-up and
188 /// sampling.
189 virtual void takeOverFrom(BaseCPU *);
190
191 /**
192 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
193 * This is a constant for the duration of the simulation.
194 */
195 int number_of_threads;
196
197 /**
198 * Vector of per-thread instruction-based event queues. Used for
199 * scheduling events based on number of instructions committed by
200 * a particular thread.
201 */
202 EventQueue **comInstEventQueue;
203
204 /**
205 * Vector of per-thread load-based event queues. Used for
206 * scheduling events based on number of loads committed by
207 *a particular thread.
208 */
209 EventQueue **comLoadEventQueue;
210
211 System *system;
212
213 Tick phase;
214
215#if FULL_SYSTEM
216 /**
217 * Serialize this object to the given output stream.
218 * @param os The stream to serialize to.
219 */
220 virtual void serialize(std::ostream &os);
221
222 /**
223 * Reconstruct the state of this object from a checkpoint.
224 * @param cp The checkpoint use.
225 * @param section The section name of this object
226 */
227 virtual void unserialize(Checkpoint *cp, const std::string &section);
228
229#endif
230
231 /**
232 * Return pointer to CPU's branch predictor (NULL if none).
233 * @return Branch predictor pointer.
234 */
235 virtual BranchPred *getBranchPred() { return NULL; };
236
237 virtual Counter totalInstructions() const { return 0; }
238
239 // Function tracing
240 private:
241 bool functionTracingEnabled;
242 std::ostream *functionTraceStream;
243 Addr currentFunctionStart;
244 Addr currentFunctionEnd;
245 Tick functionEntryTick;
246 void enableFunctionTrace();
247 void traceFunctionsInternal(Addr pc);
248
249 protected:
250 void traceFunctions(Addr pc)
251 {
252 if (functionTracingEnabled)
253 traceFunctionsInternal(pc);
254 }
255
256 private:
257 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
258
259 public:
260 static int numSimulatedCPUs() { return cpuList.size(); }
261 static Counter numSimulatedInstructions()
262 {
263 Counter total = 0;
264
265 int size = cpuList.size();
266 for (int i = 0; i < size; ++i)
267 total += cpuList[i]->totalInstructions();
268
269 return total;
270 }
271
272 public:
273 // Number of CPU cycles simulated
274 Stats::Scalar<> numCycles;
275};
276
277#endif // __CPU_BASE_HH__