1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_BASE_HH__
30#define __CPU_BASE_HH__
31
32#include <vector>
33
34#include "base/statistics.hh"
35#include "config/full_system.hh"
36#include "cpu/sampler/sampler.hh"
37#include "sim/eventq.hh"
38#include "sim/sim_object.hh"
39#include "arch/isa_traits.hh"
40
41class BranchPred;
42class CheckerCPU;
43class ExecContext;
44class System;
45
46class BaseCPU : public SimObject
47{
48 protected:
49 // CPU's clock period in terms of the number of ticks of curTime.
50 Tick clock;
51
52 public:
53 inline Tick frequency() const { return Clock::Frequency / clock; }
54 inline Tick cycles(int numCycles) const { return clock * numCycles; }
55 inline Tick curCycle() const { return curTick / clock; }
56
57#if FULL_SYSTEM
58 protected:
59 uint64_t interrupts[TheISA::NumInterruptLevels];
60 uint64_t intstatus;
61
62 public:
63 virtual void post_interrupt(int int_num, int index);
64 virtual void clear_interrupt(int int_num, int index);
65 virtual void clear_interrupts();
66 bool checkInterrupts;
67
68 bool check_interrupt(int int_num) const {
69 if (int_num > TheISA::NumInterruptLevels)
70 panic("int_num out of bounds\n");
71
72 return interrupts[int_num] != 0;
73 }
74
75 bool check_interrupts() const { return intstatus != 0; }
76 uint64_t intr_status() const { return intstatus; }
77
78 class ProfileEvent : public Event
79 {
80 private:
81 BaseCPU *cpu;
82 int interval;
83
84 public:
85 ProfileEvent(BaseCPU *cpu, int interval);
86 void process();
87 };
88 ProfileEvent *profileEvent;
89#endif
90
91 protected:
92 std::vector<ExecContext *> execContexts;
93
94 public:
95
96 /// Notify the CPU that the indicated context is now active. The
97 /// delay parameter indicates the number of ticks to wait before
98 /// executing (typically 0 or 1).
99 virtual void activateContext(int thread_num, int delay) {}
100
101 /// Notify the CPU that the indicated context is now suspended.
102 virtual void suspendContext(int thread_num) {}
103
104 /// Notify the CPU that the indicated context is now deallocated.
105 virtual void deallocateContext(int thread_num) {}
106
107 /// Notify the CPU that the indicated context is now halted.
108 virtual void haltContext(int thread_num) {}
109
110 public:
111 struct Params
112 {
113 std::string name;
114 int numberOfThreads;
115 bool deferRegistration;
116 Counter max_insts_any_thread;
117 Counter max_insts_all_threads;
118 Counter max_loads_any_thread;
119 Counter max_loads_all_threads;
120 Tick clock;
121 bool functionTrace;
122 Tick functionTraceStart;
123 System *system;
124#if FULL_SYSTEM
125 int cpu_id;
126 Tick profile;
127#endif
128 BaseCPU *checker;
129
130 Params();
131 };
132
133 const Params *params;
134
135 BaseCPU(Params *params);
136 virtual ~BaseCPU();
137
138 virtual void init();
139 virtual void startup();
140 virtual void regStats();
141
142 virtual void activateWhenReady(int tid) {};
143
144 void registerExecContexts();
145
146 /// Prepare for another CPU to take over execution. When it is
147 /// is ready (drained pipe) it signals the sampler.
148 virtual void switchOut(Sampler *);
149
150 /// Take over execution from the given CPU. Used for warm-up and
151 /// sampling.
152 virtual void takeOverFrom(BaseCPU *);
153
154 /**
155 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
156 * This is a constant for the duration of the simulation.
157 */
158 int number_of_threads;
159
160 /**
161 * Vector of per-thread instruction-based event queues. Used for
162 * scheduling events based on number of instructions committed by
163 * a particular thread.
164 */
165 EventQueue **comInstEventQueue;
166
167 /**
168 * Vector of per-thread load-based event queues. Used for
169 * scheduling events based on number of loads committed by
170 *a particular thread.
171 */
172 EventQueue **comLoadEventQueue;
173
174 System *system;
175
176#if FULL_SYSTEM
177 /**
178 * Serialize this object to the given output stream.
179 * @param os The stream to serialize to.
180 */
181 virtual void serialize(std::ostream &os);
182
183 /**
184 * Reconstruct the state of this object from a checkpoint.
185 * @param cp The checkpoint use.
186 * @param section The section name of this object
187 */
188 virtual void unserialize(Checkpoint *cp, const std::string &section);
189
190#endif
191
192 /**
193 * Return pointer to CPU's branch predictor (NULL if none).
194 * @return Branch predictor pointer.
195 */
196 virtual BranchPred *getBranchPred() { return NULL; };
197
198 virtual Counter totalInstructions() const { return 0; }
199
200 // Function tracing
201 private:
202 bool functionTracingEnabled;
203 std::ostream *functionTraceStream;
204 Addr currentFunctionStart;
205 Addr currentFunctionEnd;
206 Tick functionEntryTick;
207 void enableFunctionTrace();
208 void traceFunctionsInternal(Addr pc);
209
210 protected:
211 void traceFunctions(Addr pc)
212 {
213 if (functionTracingEnabled)
214 traceFunctionsInternal(pc);
215 }
216
217 private:
218 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
219
220 public:
221 static int numSimulatedCPUs() { return cpuList.size(); }
222 static Counter numSimulatedInstructions()
223 {
224 Counter total = 0;
225
226 int size = cpuList.size();
227 for (int i = 0; i < size; ++i)
228 total += cpuList[i]->totalInstructions();
229
230 return total;
231 }
232
233 public:
234 // Number of CPU cycles simulated
235 Stats::Scalar<> numCycles;
236};
237
238#endif // __CPU_BASE_HH__