1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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99 // @todo remove me after debugging with legion done
100 Tick instCnt;
101 // every cpu has an id, put it in the base cpu
102 // Set at initialization, only time a cpuId might change is during a
103 // takeover (which should be done from within the BaseCPU anyway,
104 // therefore no setCpuId() method is provided
105 int _cpuId;
106
107 /**
108 * Define a base class for the CPU ports (instruction and data)
109 * that is refined in the subclasses. This class handles the
110 * common cases, i.e. the functional accesses and the status
111 * changes and address range queries. The default behaviour for
112 * both atomic and timing access is to panic and the corresponding
113 * subclasses have to override these methods.
114 */

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139 void recvRangeChange();
140
141 };
142
143 public:
144 /** Reads this CPU's ID. */
145 int cpuId() { return _cpuId; }
146
147// Tick currentTick;
148 inline Tick frequency() const { return SimClock::Frequency / clock; }
149 inline Tick ticks(int numCycles) const { return clock * numCycles; }
150 inline Tick curCycle() const { return curTick() / clock; }
151 inline Tick tickToCycles(Tick val) const { return val / clock; }
152 inline void workItemBegin() { numWorkItemsStarted++; }
153 inline void workItemEnd() { numWorkItemsCompleted++; }
154 // @todo remove me after debugging with legion done

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