1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40#include "sim/eventq.hh"
41#include "sim/insttracer.hh"
42#include "mem/mem_object.hh"
43
44#if FULL_SYSTEM
45#include "arch/interrupts.hh"
46#endif
47
48class BaseCPUParams;
49class BranchPred;
50class CheckerCPU;
51class ThreadContext;
52class System;
53class Port;
54
55namespace TheISA
56{

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158
159 /// Given a Thread Context pointer return the thread num
160 int findContext(ThreadContext *tc);
161
162 /// Given a thread num get tho thread context for it
163 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
164
165 public:
166 typedef BaseCPUParams Params;
167 const Params *params() const
168 { return reinterpret_cast<const Params *>(_params); }
169 BaseCPU(Params *params);
170 virtual ~BaseCPU();
171
172 virtual void init();
173 virtual void startup();
174 virtual void regStats();
175
176 virtual void activateWhenReady(int tid) {};

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186 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
187
188 /**
189 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
190 * This is a constant for the duration of the simulation.
191 */
192 int number_of_threads;
193
194 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
195
196 /**
197 * Vector of per-thread instruction-based event queues. Used for
198 * scheduling events based on number of instructions committed by
199 * a particular thread.
200 */
201 EventQueue **comInstEventQueue;
202
203 /**

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