1c1
< # Copyright (c) 2010,2018 ARM Limited
---
> # Copyright (c) 2010, 2017-2018 ARM Limited
50,52c50,54
< 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
< 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
< 'SimdFloatMultAcc', 'SimdFloatSqrt',
---
> 'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu',
> 'SimdFloatCmp', 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc',
> 'SimdFloatMult', 'SimdFloatMultAcc', 'SimdFloatSqrt',
> 'SimdReduceAdd', 'SimdReduceAlu', 'SimdReduceCmp',
> 'SimdFloatReduceAdd', 'SimdFloatReduceCmp',
55,56c57,59
< 'SimdShaSigma3', 'MemRead', 'MemWrite',
< 'FloatMemRead', 'FloatMemWrite',
---
> 'SimdShaSigma3',
> 'SimdPredAlu',
> 'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite',