1# Copyright (c) 2010, 2017-2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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42from m5.params import *
43
44class OpClass(Enum):
45 vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
46 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatMultAcc', 'FloatDiv',
47 'FloatMisc', 'FloatSqrt',
48 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
49 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
50 'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu',
51 'SimdFloatCmp', 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc',
52 'SimdFloatMult', 'SimdFloatMultAcc', 'SimdFloatSqrt',
53 'SimdReduceAdd', 'SimdReduceAlu', 'SimdReduceCmp',
54 'SimdFloatReduceAdd', 'SimdFloatReduceCmp',
55 'SimdAes', 'SimdAesMix', 'SimdSha1Hash', 'SimdSha1Hash2',
56 'SimdSha256Hash', 'SimdSha256Hash2', 'SimdShaSigma2',
57 'SimdShaSigma3',
58 'SimdPredAlu',
59 'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite',
60 'IprAccess', 'InstPrefetch']
61
62class OpDesc(SimObject):
63 type = 'OpDesc'
64 cxx_header = "cpu/func_unit.hh"
65 opClass = Param.OpClass("type of operation")
66 opLat = Param.Cycles(1, "cycles until result is available")
67 pipelined = Param.Bool(True, "set to true when the functional unit for"
68 "this op is fully pipelined. False means not pipelined at all.")
69
70class FUDesc(SimObject):
71 type = 'FUDesc'
72 cxx_header = "cpu/func_unit.hh"
73 count = Param.Int("number of these FU's available")
74 opList = VectorParam.OpDesc("operation classes for this FU type")