1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_TYPES_HH__ 59#define __ARCH_X86_TYPES_HH__ 60
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66 67namespace X86ISA 68{ 69 //This really determines how many bytes are passed to the predecoder. 70 typedef uint64_t MachInst; 71 72 enum Prefixes { 73 NoOverride, 74 ESOverride, 75 CSOverride, 76 SSOverride, 77 DSOverride, 78 FSOverride, 79 GSOverride, 80 RexPrefix, 81 OperandSizeOverride, 82 AddressSizeOverride, 83 Lock, 84 Rep, 85 Repne 86 }; 87 88 BitUnion8(LegacyPrefixVector) 89 Bitfield<7, 4> decodeVal; 90 Bitfield<7> repne; 91 Bitfield<6> rep; 92 Bitfield<5> lock; 93 Bitfield<4> op; 94 Bitfield<3> addr; 95 //There can be only one segment override, so they share the 96 //first 3 bits in the legacyPrefixes bitfield. 97 Bitfield<2,0> seg; 98 EndBitUnion(LegacyPrefixVector) 99 100 BitUnion8(ModRM) 101 Bitfield<7,6> mod; 102 Bitfield<5,3> reg; 103 Bitfield<2,0> rm; 104 EndBitUnion(ModRM) 105 106 BitUnion8(Sib) 107 Bitfield<7,6> scale; 108 Bitfield<5,3> index; 109 Bitfield<2,0> base; 110 EndBitUnion(Sib) 111 112 BitUnion8(Rex) 113 //This bit doesn't mean anything according to the ISA, but in 114 //this implementation, it being set means an REX prefix was present. 115 Bitfield<6> present; 116 Bitfield<3> w; 117 Bitfield<2> r; 118 Bitfield<1> x; 119 Bitfield<0> b; 120 EndBitUnion(Rex) 121 122 BitUnion8(Opcode) 123 Bitfield<7,3> top5; 124 Bitfield<2,0> bottom3; 125 EndBitUnion(Opcode) 126 127 BitUnion8(OperatingMode) 128 Bitfield<3> mode; 129 Bitfield<2,0> submode; 130 EndBitUnion(OperatingMode) 131 132 enum X86Mode { 133 LongMode, 134 LegacyMode 135 }; 136 137 enum X86SubMode { 138 SixtyFourBitMode, 139 CompatabilityMode, 140 ProtectedMode, 141 Virtual8086Mode, 142 RealMode 143 }; 144 145 //The intermediate structure the x86 predecoder returns. 146 struct ExtMachInst 147 { 148 //Prefixes 149 LegacyPrefixVector legacy; 150 Rex rex; 151 //This holds all of the bytes of the opcode 152 struct 153 { 154 //The number of bytes in this opcode. Right now, we ignore that 155 //this can be 3 in some cases 156 uint8_t num; 157 //The first byte detected in a 2+ byte opcode. Should be 0xF0. 158 uint8_t prefixA; 159 //The second byte detected in a 3+ byte opcode. Could be 0xF0 for 160 //3dnow instructions, or 0x38-0x3F for some SSE instructions. 161 uint8_t prefixB; 162 //The main opcode byte. The highest addressed byte in the opcode. 163 Opcode op; 164 } opcode; 165 //Modifier bytes 166 ModRM modRM; 167 Sib sib; 168 //Immediate fields 169 uint64_t immediate; 170 uint64_t displacement; 171 172 //The effective operand size. 173 uint8_t opSize; 174 //The effective address size. 175 uint8_t addrSize; 176 //The effective stack size. 177 uint8_t stackSize; 178 179 //Mode information 180 OperatingMode mode; 181 }; 182 183 inline static std::ostream & 184 operator << (std::ostream & os, const ExtMachInst & emi) 185 { 186 ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t" 187 "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t" 188 "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t" 189 "modRM = %#x,\n\tsib = %#x,\n\t" 190 "immediate = %#x,\n\tdisplacement = %#x\n}\n", 191 (uint8_t)emi.legacy, (uint8_t)emi.rex, 192 emi.opcode.num, (uint8_t)emi.opcode.op, 193 emi.opcode.prefixA, emi.opcode.prefixB, 194 (uint8_t)emi.modRM, (uint8_t)emi.sib, 195 emi.immediate, emi.displacement); 196 return os; 197 } 198 199 inline static bool 200 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) 201 { 202 if(emi1.legacy != emi2.legacy) 203 return false; 204 if(emi1.rex != emi2.rex) 205 return false; 206 if(emi1.opcode.num != emi2.opcode.num) 207 return false; 208 if(emi1.opcode.op != emi2.opcode.op) 209 return false; 210 if(emi1.opcode.prefixA != emi2.opcode.prefixA) 211 return false; 212 if(emi1.opcode.prefixB != emi2.opcode.prefixB) 213 return false; 214 if(emi1.modRM != emi2.modRM) 215 return false; 216 if(emi1.sib != emi2.sib) 217 return false; 218 if(emi1.immediate != emi2.immediate) 219 return false; 220 if(emi1.displacement != emi2.displacement) 221 return false; 222 if(emi1.mode != emi2.mode) 223 return false; 224 if(emi1.opSize != emi2.opSize) 225 return false; 226 if(emi1.addrSize != emi2.addrSize) 227 return false; 228 if(emi1.stackSize != emi2.stackSize) 229 return false; 230 return true; 231 } 232 233 typedef uint64_t IntReg; 234 //XXX Should this be a 128 bit structure for XMM memory ops? 235 typedef uint64_t LargestRead; 236 typedef uint64_t MiscReg; 237 238 //These floating point types are correct for mmx, but not 239 //technically for x87 (80 bits) or at all for xmm (128 bits) 240 typedef double FloatReg; 241 typedef uint64_t FloatRegBits; 242 typedef union 243 { 244 IntReg intReg; 245 FloatReg fpReg; 246 MiscReg ctrlReg; 247 } AnyReg; 248 249 typedef uint16_t RegIndex; 250 251 struct CoreSpecific { 252 int core_type; 253 }; 254}; 255 256#endif // __ARCH_X86_TYPES_HH__
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