1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_TYPES_HH__ 59#define __ARCH_X86_TYPES_HH__ 60 61#include <inttypes.h>
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62#include <iostream> |
63 64namespace X86ISA 65{ 66 //This really determines how many bytes are passed to the predecoder. 67 typedef uint64_t MachInst;
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68 69 enum Prefixes { 70 NoOverride = 0, 71 CSOverride = 1, 72 DSOverride = 2, 73 ESOverride = 3, 74 FSOverride = 4, 75 GSOverride = 5, 76 SSOverride = 6, 77 //The Rex prefix obviously doesn't fit in with the above, but putting 78 //it here lets us save double the space the enums take up. 79 Rex = 7, 80 //There can be only one segment override, so they share the 81 //first 3 bits in the legacyPrefixes bitfield. 82 SegmentOverride = 0x7, 83 OperandSizeOverride = 8, 84 AddressSizeOverride = 16, 85 Lock = 32, 86 Rep = 64, 87 Repne = 128 88 }; 89 |
90 //The intermediate structure the x86 predecoder returns. 91 struct ExtMachInst 92 {
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70 //Empty for now...
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93 public: //XXX These should be hidden in the future 94 95 uint8_t legacyPrefixes; 96 uint8_t rexPrefix; 97 bool twoByteOpcode; 98 uint8_t opcode; 99 uint64_t immediate; 100 uint64_t displacement; 101 102 public: 103 104 //These are to pacify the decoder for now. This will go away once 105 //it can handle non integer inputs, and in the mean time allow me to 106 //excercise the predecoder a little. 107 operator unsigned int() 108 { 109 return 0; 110 } 111 112 ExtMachInst(unsigned int) 113 {;} 114 115 ExtMachInst() 116 {;} |
117 }; 118
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73 bool operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
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119 inline static std::ostream & 120 operator << (std::ostream & os, const ExtMachInst & emi) |
121 {
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122 os << "{X86 ExtMachInst}"; 123 return os; 124 } 125 126 inline static bool 127 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) 128 { |
129 //Since this is empty, it's always equal 130 return true; 131 } 132 133 typedef uint64_t IntReg; 134 //XXX Should this be a 128 bit structure for XMM memory ops? 135 typedef uint64_t LargestRead; 136 typedef uint64_t MiscReg; 137 138 //These floating point types are correct for mmx, but not 139 //technically for x87 (80 bits) or at all for xmm (128 bits) 140 typedef double FloatReg; 141 typedef uint64_t FloatRegBits; 142 typedef union 143 { 144 IntReg intReg; 145 FloatReg fpReg; 146 MiscReg ctrlReg; 147 } AnyReg; 148 149 //XXX This is very hypothetical. X87 instructions would need to 150 //change their "context" constantly. It's also not clear how 151 //this would be handled as far as out of order execution. 152 //Maybe x87 instructions are in order? 153 enum RegContextParam 154 { 155 CONTEXT_X87_TOP 156 }; 157 158 typedef int RegContextVal; 159 160 typedef uint8_t RegIndex; 161}; 162 163#endif // __ARCH_X86_TYPES_HH__
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