1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_X86_TYPES_HH__ 41#define __ARCH_X86_TYPES_HH__ 42 43#include <iostream> 44 45#include "arch/generic/types.hh" 46#include "base/bitunion.hh" 47#include "base/cprintf.hh" 48#include "base/types.hh" 49#include "sim/serialize.hh" 50 51namespace X86ISA 52{ 53 //This really determines how many bytes are passed to the decoder. 54 typedef uint64_t MachInst; 55 56 enum Prefixes { 57 NoOverride, 58 ESOverride, 59 CSOverride, 60 SSOverride, 61 DSOverride, 62 FSOverride, 63 GSOverride, 64 RexPrefix, 65 OperandSizeOverride, 66 AddressSizeOverride, 67 Lock, 68 Rep, 69 Repne, 70 Vex2Prefix, 71 Vex3Prefix, 72 XopPrefix, 73 }; 74 75 BitUnion8(LegacyPrefixVector) 76 Bitfield<7, 4> decodeVal; 77 Bitfield<7> repne; 78 Bitfield<6> rep; 79 Bitfield<5> lock; 80 Bitfield<4> op; 81 Bitfield<3> addr; 82 //There can be only one segment override, so they share the 83 //first 3 bits in the legacyPrefixes bitfield. 84 Bitfield<2,0> seg; 85 EndBitUnion(LegacyPrefixVector) 86 87 BitUnion8(ModRM) 88 Bitfield<7,6> mod; 89 Bitfield<5,3> reg; 90 Bitfield<2,0> rm; 91 EndBitUnion(ModRM) 92 93 BitUnion8(Sib) 94 Bitfield<7,6> scale; 95 Bitfield<5,3> index; 96 Bitfield<2,0> base; 97 EndBitUnion(Sib) 98 99 BitUnion8(Rex) 100 //This bit doesn't mean anything according to the ISA, but in 101 //this implementation, it being set means an REX prefix was present. 102 Bitfield<6> present; 103 Bitfield<3> w; 104 Bitfield<2> r; 105 Bitfield<1> x; 106 Bitfield<0> b; 107 EndBitUnion(Rex) 108
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109 BitUnion(uint32_t, ThreeByteVex)
110 Bitfield<7,0> zero;
111 SubBitUnion(first, 15, 8)
112 // Inverted one-bit extension of ModRM reg field
113 Bitfield<15> r;
114 // Inverted one-bit extension of SIB index field
115 Bitfield<14> x;
116 // Inverted one-bit extension, r/m field or SIB base field
117 Bitfield<13> b;
118 // Opcode map select
119 Bitfield<12, 8> map_select;
120 EndSubBitUnion(first)
121 SubBitUnion(second, 23, 16)
122 // Default operand size override for a general purpose register to
123 // 64-bit size in 64-bit mode; operand configuration specifier for
124 // certain YMM/XMM-based operations.
125 Bitfield<23> w;
126 // Source or destination register selector, in ones' complement
127 // format
128 Bitfield<22, 19> vvvv;
129 // Vector length specifier
130 Bitfield<18> l;
131 // Implied 66, F2, or F3 opcode extension
132 Bitfield<17, 16> pp;
133 EndSubBitUnion(second)
134 EndBitUnion(ThreeByteVex)
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109 BitUnion8(Vex2Of3) 110 // Inverted bits from the REX prefix. 111 Bitfield<7> r; 112 Bitfield<6> x; 113 Bitfield<5> b; 114 // Selector for what would be two or three byte opcode types. 115 Bitfield<4, 0> m; 116 EndBitUnion(Vex2Of3) |
117
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136 BitUnion16(TwoByteVex)
137 Bitfield<7,0> zero;
138 SubBitUnion(first, 15, 8)
139 // Inverted one-bit extension of ModRM reg field
140 Bitfield<15> r;
141 // Source or destination register selector, in ones' complement
142 // format
143 Bitfield<14, 11> vvvv;
144 // Vector length specifier
145 Bitfield<10> l;
146 // Implied 66, F2, or F3 opcode extension
147 Bitfield<9, 8> pp;
148 EndSubBitUnion(first)
149 EndBitUnion(TwoByteVex)
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118 BitUnion8(Vex3Of3) 119 // Bit from the REX prefix. 120 Bitfield<7> w; 121 // Inverted extra register index. 122 Bitfield<6, 3> v; 123 // Vector length specifier. 124 Bitfield<2> l; 125 // Implied 66, F2, or F3 opcode prefix. 126 Bitfield<1, 0> p; 127 EndBitUnion(Vex3Of3) |
128
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129 BitUnion8(Vex2Of2) 130 // Inverted bit from the REX prefix. 131 Bitfield<7> r; 132 // Inverted extra register index. 133 Bitfield<6, 3> v; 134 // Vector length specifier 135 Bitfield<2> l; 136 // Implied 66, F2, or F3 opcode prefix. 137 Bitfield<1, 0> p; 138 EndBitUnion(Vex2Of2) 139 140 BitUnion8(VexInfo) 141 // Extra register index. 142 Bitfield<6, 3> v; 143 // Vector length specifier. 144 Bitfield<2> l; 145 // Whether the VEX prefix was used. 146 Bitfield<0> present; 147 EndBitUnion(VexInfo) 148 |
149 enum OpcodeType { 150 BadOpcode, 151 OneByteOpcode, 152 TwoByteOpcode, 153 ThreeByte0F38Opcode, 154 ThreeByte0F3AOpcode,
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157 Vex,
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155 }; 156 157 static inline const char * 158 opcodeTypeToStr(OpcodeType type) 159 { 160 switch (type) { 161 case BadOpcode: 162 return "bad"; 163 case OneByteOpcode: 164 return "one byte"; 165 case TwoByteOpcode: 166 return "two byte"; 167 case ThreeByte0F38Opcode: 168 return "three byte 0f38"; 169 case ThreeByte0F3AOpcode: 170 return "three byte 0f3a";
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174 case Vex:
175 return "vex";
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171 default: 172 return "unrecognized!"; 173 } 174 } 175 176 BitUnion8(Opcode) 177 Bitfield<7,3> top5; 178 Bitfield<2,0> bottom3; 179 EndBitUnion(Opcode) 180 181 BitUnion8(OperatingMode) 182 Bitfield<3> mode; 183 Bitfield<2,0> submode; 184 EndBitUnion(OperatingMode) 185 186 enum X86Mode { 187 LongMode, 188 LegacyMode 189 }; 190 191 enum X86SubMode { 192 SixtyFourBitMode, 193 CompatabilityMode, 194 ProtectedMode, 195 Virtual8086Mode, 196 RealMode 197 }; 198 199 //The intermediate structure used by the x86 decoder. 200 struct ExtMachInst 201 { 202 //Prefixes 203 LegacyPrefixVector legacy; 204 Rex rex;
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210 // We use the following field for encoding both two byte and three byte
211 // escape sequences
212 ThreeByteVex vex;
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205 VexInfo vex; |
206 207 //This holds all of the bytes of the opcode 208 struct 209 { 210 OpcodeType type; 211 //The main opcode byte. The highest addressed byte in the opcode. 212 Opcode op; 213 } opcode; 214 //Modifier bytes 215 ModRM modRM; 216 Sib sib; 217 //Immediate fields 218 uint64_t immediate; 219 uint64_t displacement; 220 221 //The effective operand size. 222 uint8_t opSize; 223 //The effective address size. 224 uint8_t addrSize; 225 //The effective stack size. 226 uint8_t stackSize; 227 //The size of the displacement 228 uint8_t dispSize; 229 230 //Mode information 231 OperatingMode mode; 232 }; 233 234 inline static std::ostream & 235 operator << (std::ostream & os, const ExtMachInst & emi) 236 { 237 ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t" 238 "vex/xop = %#x,\n\t" 239 "op = {\n\t\ttype = %s,\n\t\top = %#x,\n\t\t},\n\t" 240 "modRM = %#x,\n\tsib = %#x,\n\t" 241 "immediate = %#x,\n\tdisplacement = %#x\n\t" 242 "dispSize = %d}\n", 243 (uint8_t)emi.legacy, (uint8_t)emi.rex,
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251 (uint32_t)emi.vex,
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244 (uint8_t)emi.vex, |
245 opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op, 246 (uint8_t)emi.modRM, (uint8_t)emi.sib, 247 emi.immediate, emi.displacement, emi.dispSize); 248 return os; 249 } 250 251 inline static bool 252 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) 253 { 254 if (emi1.legacy != emi2.legacy) 255 return false; 256 if (emi1.rex != emi2.rex) 257 return false;
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258 if (emi1.vex != emi2.vex) 259 return false; |
260 if (emi1.opcode.type != emi2.opcode.type) 261 return false; 262 if (emi1.opcode.op != emi2.opcode.op) 263 return false; 264 if (emi1.modRM != emi2.modRM) 265 return false; 266 if (emi1.sib != emi2.sib) 267 return false; 268 if (emi1.immediate != emi2.immediate) 269 return false; 270 if (emi1.displacement != emi2.displacement) 271 return false; 272 if (emi1.mode != emi2.mode) 273 return false; 274 if (emi1.opSize != emi2.opSize) 275 return false; 276 if (emi1.addrSize != emi2.addrSize) 277 return false; 278 if (emi1.stackSize != emi2.stackSize) 279 return false; 280 if (emi1.dispSize != emi2.dispSize) 281 return false; 282 return true; 283 } 284 285 class PCState : public GenericISA::UPCState<MachInst> 286 { 287 protected: 288 typedef GenericISA::UPCState<MachInst> Base; 289 290 uint8_t _size; 291 292 public: 293 void 294 set(Addr val) 295 { 296 Base::set(val); 297 _size = 0; 298 } 299 300 PCState() {} 301 PCState(Addr val) { set(val); } 302 303 void 304 setNPC(Addr val) 305 { 306 Base::setNPC(val); 307 _size = 0; 308 } 309 310 uint8_t size() const { return _size; } 311 void size(uint8_t newSize) { _size = newSize; } 312 313 bool 314 branching() const 315 { 316 return (this->npc() != this->pc() + size()) || 317 (this->nupc() != this->upc() + 1); 318 } 319 320 void 321 advance() 322 { 323 Base::advance(); 324 _size = 0; 325 } 326 327 void 328 uEnd() 329 { 330 Base::uEnd(); 331 _size = 0; 332 } 333 334 void 335 serialize(CheckpointOut &cp) const 336 { 337 Base::serialize(cp); 338 SERIALIZE_SCALAR(_size); 339 } 340 341 void 342 unserialize(CheckpointIn &cp) 343 { 344 Base::unserialize(cp); 345 UNSERIALIZE_SCALAR(_size); 346 } 347 }; 348 349} 350 351namespace std { 352 template<> 353 struct hash<X86ISA::ExtMachInst> { 354 size_t operator()(const X86ISA::ExtMachInst &emi) const {
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360 return (((uint64_t)emi.legacy << 40) |
361 ((uint64_t)emi.rex << 32) |
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355 return (((uint64_t)emi.legacy << 48) | 356 ((uint64_t)emi.rex << 40) | 357 ((uint64_t)emi.vex << 32) | |
358 ((uint64_t)emi.modRM << 24) | 359 ((uint64_t)emi.sib << 16) | 360 ((uint64_t)emi.opcode.type << 8) | 361 ((uint64_t)emi.opcode.op)) ^ 362 emi.immediate ^ emi.displacement ^ 363 emi.mode ^ 364 emi.opSize ^ emi.addrSize ^ 365 emi.stackSize ^ emi.dispSize; 366 }; 367 }; 368} 369 370// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR 371// and UNSERIALIZE_SCALAR. 372template <> 373void 374paramOut(CheckpointOut &cp, const std::string &name, 375 const X86ISA::ExtMachInst &machInst); 376template <> 377void 378paramIn(CheckpointIn &cp, const std::string &name, 379 X86ISA::ExtMachInst &machInst); 380 381#endif // __ARCH_X86_TYPES_HH__
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