109,134c109,116
< BitUnion(uint32_t, ThreeByteVex)
< Bitfield<7,0> zero;
< SubBitUnion(first, 15, 8)
< // Inverted one-bit extension of ModRM reg field
< Bitfield<15> r;
< // Inverted one-bit extension of SIB index field
< Bitfield<14> x;
< // Inverted one-bit extension, r/m field or SIB base field
< Bitfield<13> b;
< // Opcode map select
< Bitfield<12, 8> map_select;
< EndSubBitUnion(first)
< SubBitUnion(second, 23, 16)
< // Default operand size override for a general purpose register to
< // 64-bit size in 64-bit mode; operand configuration specifier for
< // certain YMM/XMM-based operations.
< Bitfield<23> w;
< // Source or destination register selector, in ones' complement
< // format
< Bitfield<22, 19> vvvv;
< // Vector length specifier
< Bitfield<18> l;
< // Implied 66, F2, or F3 opcode extension
< Bitfield<17, 16> pp;
< EndSubBitUnion(second)
< EndBitUnion(ThreeByteVex)
---
> BitUnion8(Vex2Of3)
> // Inverted bits from the REX prefix.
> Bitfield<7> r;
> Bitfield<6> x;
> Bitfield<5> b;
> // Selector for what would be two or three byte opcode types.
> Bitfield<4, 0> m;
> EndBitUnion(Vex2Of3)
136,149c118,127
< BitUnion16(TwoByteVex)
< Bitfield<7,0> zero;
< SubBitUnion(first, 15, 8)
< // Inverted one-bit extension of ModRM reg field
< Bitfield<15> r;
< // Source or destination register selector, in ones' complement
< // format
< Bitfield<14, 11> vvvv;
< // Vector length specifier
< Bitfield<10> l;
< // Implied 66, F2, or F3 opcode extension
< Bitfield<9, 8> pp;
< EndSubBitUnion(first)
< EndBitUnion(TwoByteVex)
---
> BitUnion8(Vex3Of3)
> // Bit from the REX prefix.
> Bitfield<7> w;
> // Inverted extra register index.
> Bitfield<6, 3> v;
> // Vector length specifier.
> Bitfield<2> l;
> // Implied 66, F2, or F3 opcode prefix.
> Bitfield<1, 0> p;
> EndBitUnion(Vex3Of3)
150a129,148
> BitUnion8(Vex2Of2)
> // Inverted bit from the REX prefix.
> Bitfield<7> r;
> // Inverted extra register index.
> Bitfield<6, 3> v;
> // Vector length specifier
> Bitfield<2> l;
> // Implied 66, F2, or F3 opcode prefix.
> Bitfield<1, 0> p;
> EndBitUnion(Vex2Of2)
>
> BitUnion8(VexInfo)
> // Extra register index.
> Bitfield<6, 3> v;
> // Vector length specifier.
> Bitfield<2> l;
> // Whether the VEX prefix was used.
> Bitfield<0> present;
> EndBitUnion(VexInfo)
>
157d154
< Vex,
174,175d170
< case Vex:
< return "vex";
210,212c205
< // We use the following field for encoding both two byte and three byte
< // escape sequences
< ThreeByteVex vex;
---
> VexInfo vex;
251c244
< (uint32_t)emi.vex,
---
> (uint8_t)emi.vex,
264a258,259
> if (emi1.vex != emi2.vex)
> return false;
360,361c355,357
< return (((uint64_t)emi.legacy << 40) |
< ((uint64_t)emi.rex << 32) |
---
> return (((uint64_t)emi.legacy << 48) |
> ((uint64_t)emi.rex << 40) |
> ((uint64_t)emi.vex << 32) |