1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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101 //this implementation, it being set means an REX prefix was present.
102 Bitfield<6> present;
103 Bitfield<3> w;
104 Bitfield<2> r;
105 Bitfield<1> x;
106 Bitfield<0> b;
107 EndBitUnion(Rex)
108
109 BitUnion(uint32_t, ThreeByteVex)
110 Bitfield<7,0> zero;
111 SubBitUnion(first, 15, 8)
112 // Inverted one-bit extension of ModRM reg field
113 Bitfield<15> r;
114 // Inverted one-bit extension of SIB index field
115 Bitfield<14> x;
116 // Inverted one-bit extension, r/m field or SIB base field
117 Bitfield<13> b;
118 // Opcode map select
119 Bitfield<12, 8> map_select;
120 EndSubBitUnion(first)
121 SubBitUnion(second, 23, 16)
122 // Default operand size override for a general purpose register to
123 // 64-bit size in 64-bit mode; operand configuration specifier for
124 // certain YMM/XMM-based operations.
125 Bitfield<23> w;
126 // Source or destination register selector, in ones' complement
127 // format
128 Bitfield<22, 19> vvvv;
129 // Vector length specifier
130 Bitfield<18> l;
131 // Implied 66, F2, or F3 opcode extension
132 Bitfield<17, 16> pp;
133 EndSubBitUnion(second)
134 EndBitUnion(ThreeByteVex)
135
136 BitUnion16(TwoByteVex)
137 Bitfield<7,0> zero;
138 SubBitUnion(first, 15, 8)
139 // Inverted one-bit extension of ModRM reg field
140 Bitfield<15> r;
141 // Source or destination register selector, in ones' complement
142 // format
143 Bitfield<14, 11> vvvv;
144 // Vector length specifier
145 Bitfield<10> l;
146 // Implied 66, F2, or F3 opcode extension
147 Bitfield<9, 8> pp;
148 EndSubBitUnion(first)
149 EndBitUnion(TwoByteVex)
150
151 enum OpcodeType {
152 BadOpcode,
153 OneByteOpcode,
154 TwoByteOpcode,
155 ThreeByte0F38Opcode,
156 ThreeByte0F3AOpcode,
157 Vex,
158 };
159
160 static inline const char *
161 opcodeTypeToStr(OpcodeType type)
162 {
163 switch (type) {
164 case BadOpcode:
165 return "bad";
166 case OneByteOpcode:
167 return "one byte";
168 case TwoByteOpcode:
169 return "two byte";
170 case ThreeByte0F38Opcode:
171 return "three byte 0f38";
172 case ThreeByte0F3AOpcode:
173 return "three byte 0f3a";
174 case Vex:
175 return "vex";
176 default:
177 return "unrecognized!";
178 }
179 }
180
181 BitUnion8(Opcode)
182 Bitfield<7,3> top5;
183 Bitfield<2,0> bottom3;

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202 };
203
204 //The intermediate structure used by the x86 decoder.
205 struct ExtMachInst
206 {
207 //Prefixes
208 LegacyPrefixVector legacy;
209 Rex rex;
210 // We use the following field for encoding both two byte and three byte
211 // escape sequences
212 ThreeByteVex vex;
213
214 //This holds all of the bytes of the opcode
215 struct
216 {
217 OpcodeType type;
218 //The main opcode byte. The highest addressed byte in the opcode.
219 Opcode op;
220 } opcode;

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243 {
244 ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
245 "vex/xop = %#x,\n\t"
246 "op = {\n\t\ttype = %s,\n\t\top = %#x,\n\t\t},\n\t"
247 "modRM = %#x,\n\tsib = %#x,\n\t"
248 "immediate = %#x,\n\tdisplacement = %#x\n\t"
249 "dispSize = %d}\n",
250 (uint8_t)emi.legacy, (uint8_t)emi.rex,
251 (uint32_t)emi.vex,
252 opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op,
253 (uint8_t)emi.modRM, (uint8_t)emi.sib,
254 emi.immediate, emi.displacement, emi.dispSize);
255 return os;
256 }
257
258 inline static bool
259 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
260 {
261 if (emi1.legacy != emi2.legacy)
262 return false;
263 if (emi1.rex != emi2.rex)
264 return false;
265 if (emi1.opcode.type != emi2.opcode.type)
266 return false;
267 if (emi1.opcode.op != emi2.opcode.op)
268 return false;
269 if (emi1.modRM != emi2.modRM)
270 return false;
271 if (emi1.sib != emi2.sib)
272 return false;

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352 };
353
354}
355
356namespace std {
357 template<>
358 struct hash<X86ISA::ExtMachInst> {
359 size_t operator()(const X86ISA::ExtMachInst &emi) const {
360 return (((uint64_t)emi.legacy << 40) |
361 ((uint64_t)emi.rex << 32) |
362 ((uint64_t)emi.modRM << 24) |
363 ((uint64_t)emi.sib << 16) |
364 ((uint64_t)emi.opcode.type << 8) |
365 ((uint64_t)emi.opcode.op)) ^
366 emi.immediate ^ emi.displacement ^
367 emi.mode ^
368 emi.opSize ^ emi.addrSize ^
369 emi.stackSize ^ emi.dispSize;

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