microasm.isa (5121:a5f3cfdc4ee5) microasm.isa (5149:356e00996637)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// Redistribution and use of this software in source and binary forms,
7// with or without modification, are permitted provided that the
8// following conditions are met:

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101 assembler.symbols.update(symbols)
102
103 # Short hand for common scale-index-base combinations.
104 assembler.symbols["sib"] = \
105 [symbols["scale"], symbols["index"], symbols["base"]]
106 assembler.symbols["riprel"] = \
107 ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
108
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// Redistribution and use of this software in source and binary forms,
7// with or without modification, are permitted provided that the
8// following conditions are met:

--- 92 unchanged lines hidden (view full) ---

101 assembler.symbols.update(symbols)
102
103 # Short hand for common scale-index-base combinations.
104 assembler.symbols["sib"] = \
105 [symbols["scale"], symbols["index"], symbols["base"]]
106 assembler.symbols["riprel"] = \
107 ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
108
109 # This segment selects an internal address space mapped to MSRs,
110 # CPUID info, etc.
111 assembler.symbols["intseg"] = "NUM_SEGMENTREGS"
112
109 for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
110 assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
111
112 for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'):
113 assembler.symbols[flag] = flag + "Bit"
114
115 for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
116 'MSTRZ', 'STRZ', 'MSTRC',

--- 29 unchanged lines hidden --- 		113 for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
114 assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
115
116 for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'):
117 assembler.symbols[flag] = flag + "Bit"
118
119 for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
120 'MSTRZ', 'STRZ', 'MSTRC',

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