1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 The Hewlett-Packard Development Company 4// All rights reserved. 5// 6// Redistribution and use of this software in source and binary forms, 7// with or without modification, are permitted provided that the 8// following conditions are met: --- 75 unchanged lines hidden (view full) --- 84 "regm" : "env.regm", 85 "imm" : "IMMEDIATE", 86 "disp" : "DISPLACEMENT", 87 "seg" : "env.seg", 88 "scale" : "env.scale", 89 "index" : "env.index", 90 "base" : "env.base", 91 "dsz" : "env.dataSize", |
92 "asz" : "env.addressSize", |
93 "ssz" : "env.stackSize" 94 } 95 assembler.symbols.update(symbols) 96 97 # Short hand for common scale-index-base combinations. 98 assembler.symbols["sib"] = \ 99 [symbols["scale"], symbols["index"], symbols["base"]] 100 assembler.symbols["riprel"] = \ 101 ["1", assembler.symbols["t0"], assembler.symbols["t7"]] 102 103 for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): 104 assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() 105 106 for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'): 107 assembler.symbols[flag] = flag + "Bit" 108 109 for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF', |
110 'MSTRZ', 'STRZ', 'MSTRC', |
111 'OF', 'CF', 'ZF', 'CvZF', 112 'SF', 'PF', 'SxOF', 'SxOvZF'): 113 assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond 114 assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond |
115 assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF" 116 assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF" |
117 118 assembler.symbols["CTrue"] = "ConditionTests::True" 119 assembler.symbols["CFalse"] = "ConditionTests::False" 120 121 # Code literal which forces a default 64 bit operand size in 64 bit mode. 122 assembler.symbols["oszIn64Override"] = ''' 123 if (machInst.mode.submode == SixtyFourBitMode && 124 env.dataSize == 4) 125 env.dataSize = 8; 126 ''' 127 128 macroopDict = assembler.assemble(microcode) 129}}; |