1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40//Include the definitions of the micro ops.
41//These are python representations of static insts which stand on their own
42//and make up an internal instruction set. They are used by the micro
43//assembler.
44##include "microops/microops.isa"
45
46//Include code to build macroops in both C++ and python.
47##include "macroop.isa"
48
49//Include code to fill out the microcode ROM in both C++ and python.
50##include "rom.isa"
51
52let {{
53 import sys
54 sys.path[0:0] = ["src/arch/x86/isa/"]
55 from insts import microcode
56 # print microcode
57 from micro_asm import MicroAssembler, Rom_Macroop
58 mainRom = X86MicrocodeRom('main ROM')
59 assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
60
61 def regIdx(idx):
62 return "InstRegIndex(%s)" % idx
63
64 assembler.symbols["regIdx"] = regIdx
65
66 # Add in symbols for the microcode registers
67 for num in range(16):
68 assembler.symbols["t%d" % num] = regIdx("NUM_INTREGS+%d" % num)
69 for num in range(8):
70 assembler.symbols["ufp%d" % num] = \
71 regIdx("FLOATREG_MICROFP(%d)" % num)
72 # Add in symbols for the segment descriptor registers
73 for letter in ("C", "D", "E", "F", "G", "H", "S"):
74 assembler.symbols["%ss" % letter.lower()] = \
75 regIdx("SEGMENT_REG_%sS" % letter)
76
77 # Add in symbols for the various checks of segment selectors.
78 for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck",
79 "SoftIntGateCheck", "SSCheck", "IretCheck", "IntCSCheck",
80 "TRCheck", "TSSCheck", "InGDTCheck", "LDTCheck"):
81 assembler.symbols[check] = "Seg%s" % check
82
83 for reg in ("TR", "IDTR"):
84 assembler.symbols[reg.lower()] = regIdx("SYS_SEGMENT_REG_%s" % reg)
85
86 for reg in ("TSL", "TSG"):
87 assembler.symbols[reg.lower()] = regIdx("SEGMENT_REG_%s" % reg)
88
89 # Miscellaneous symbols
90 symbols = {
91 "reg" : regIdx("env.reg"),
92 "xmml" : regIdx("FLOATREG_XMM_LOW(env.reg)"),
93 "xmmh" : regIdx("FLOATREG_XMM_HIGH(env.reg)"),
94 "regm" : regIdx("env.regm"),
95 "xmmlm" : regIdx("FLOATREG_XMM_LOW(env.regm)"),
96 "xmmhm" : regIdx("FLOATREG_XMM_HIGH(env.regm)"),
97 "mmx" : regIdx("FLOATREG_MMX(env.reg)"),
98 "mmxm" : regIdx("FLOATREG_MMX(env.regm)"),
99 "imm" : "adjustedImm",
100 "disp" : "adjustedDisp",
101 "seg" : regIdx("env.seg"),
102 "scale" : "env.scale",
103 "index" : regIdx("env.index"),
104 "base" : regIdx("env.base"),
105 "dsz" : "env.dataSize",
106 "asz" : "env.addressSize",
107 "ssz" : "env.stackSize"
108 }
109 assembler.symbols.update(symbols)
110
111 assembler.symbols["ldsz"] = \
112 "((env.dataSize == 8) ? 3 : (env.dataSize == 4) ? 2 : 1)"
113
114 assembler.symbols["lasz"] = \
115 "((env.addressSize == 8) ? 3 : (env.addressSize == 4) ? 2 : 1)"
116
117 assembler.symbols["lssz"] = \
118 "((env.stackSize == 8) ? 3 : (env.stackSize == 4) ? 2 : 1)"
119
120 # Short hand for common scale-index-base combinations.
121 assembler.symbols["sib"] = \
122 [symbols["scale"], symbols["index"], symbols["base"]]
123 assembler.symbols["riprel"] = \
124 ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
125
126 # This segment selects an internal address space mapped to MSRs,
127 # CPUID info, etc.
128 assembler.symbols["intseg"] = regIdx("SEGMENT_REG_MS")
129 # This segment always has base 0, and doesn't imply any special handling
130 # like the internal segment above
131 assembler.symbols["flatseg"] = regIdx("SEGMENT_REG_LS")
132
133 for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di', \
134 '8', '9', '10', '11', '12', '13', '14', '15'):
135 assembler.symbols["r%s" % reg] = \
136 regIdx("INTREG_R%s" % reg.upper())
137
138 for reg in ('ah', 'bh', 'ch', 'dh'):
139 assembler.symbols[reg] = \
140 regIdx("INTREG_FOLDED(INTREG_%s, IntFoldBit)" % reg.upper())
141
142 for reg in range(16):
143 assembler.symbols["cr%d" % reg] = regIdx("MISCREG_CR%d" % reg)
144
145 for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \
146 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'):
147 assembler.symbols[flag] = flag + "Bit"
148
149 for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
150 'MSTRZ', 'STRZ', 'MSTRC',
151 'OF', 'CF', 'ZF', 'CvZF',
152 'SF', 'PF', 'SxOF', 'SxOvZF'):
153 assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
154 assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
155 assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
156 assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
157
158 assembler.symbols["CTrue"] = "ConditionTests::True"
159 assembler.symbols["CFalse"] = "ConditionTests::False"
160
161 for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip',
162 'star', 'lstar', 'cstar', 'sf_mask',
163 'kernel_gs_base'):
164 assembler.symbols[reg] = regIdx("MISCREG_%s" % reg.upper())
165
166 for flag in ('Scalar', 'MultHi', 'Signed'):
167 assembler.symbols[flag] = 'Media%sOp' % flag
168
169 # Code literal which forces a default 64 bit operand size in 64 bit mode.
170 assembler.symbols["oszIn64Override"] = '''
171 if (machInst.mode.submode == SixtyFourBitMode &&
172 env.dataSize == 4)
173 env.dataSize = 8;
174 '''
175
176 assembler.symbols["maxOsz"] = '''
177 if (machInst.mode.submode == SixtyFourBitMode)
178 env.dataSize = 8;
179 else
180 env.dataSize = 4;
181 '''
182
183 def trimImm(width):
184 return "adjustedImm = adjustedImm & mask(%s);" % width
185
186 assembler.symbols["trimImm"] = trimImm
187
188 def labeler(labelStr):
189 return "label_%s" % labelStr
190
191 assembler.symbols["label"] = labeler
192
193 def rom_labeler(labelStr):
194 return "romMicroPC(RomLabels::extern_label_%s)" % labelStr
195
196 assembler.symbols["rom_label"] = rom_labeler
197
198 def rom_local_labeler(labelStr):
199 return "romMicroPC(RomLabels::label_%s)" % labelStr
200
201 assembler.symbols["rom_local_label"] = rom_local_labeler
202
203 def stack_index(index):
204 return regIdx("NUM_FLOATREGS + (((%s) + 8) %% 8)" % index)
205
206 assembler.symbols["st"] = stack_index
207 assembler.symbols["sti"] = stack_index("env.reg")
208 assembler.symbols["stim"] = stack_index("env.regm")
209
210 def readFpReg(reg_name):
211 return regIdx("MISCREG_%s" % reg_name)
212
213 assembler.symbols["fsw"] = readFpReg("FSW")
214 assembler.symbols["fcw"] = readFpReg("FCW")
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40//Include the definitions of the micro ops.
41//These are python representations of static insts which stand on their own
42//and make up an internal instruction set. They are used by the micro
43//assembler.
44##include "microops/microops.isa"
45
46//Include code to build macroops in both C++ and python.
47##include "macroop.isa"
48
49//Include code to fill out the microcode ROM in both C++ and python.
50##include "rom.isa"
51
52let {{
53 import sys
54 sys.path[0:0] = ["src/arch/x86/isa/"]
55 from insts import microcode
56 # print microcode
57 from micro_asm import MicroAssembler, Rom_Macroop
58 mainRom = X86MicrocodeRom('main ROM')
59 assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
60
61 def regIdx(idx):
62 return "InstRegIndex(%s)" % idx
63
64 assembler.symbols["regIdx"] = regIdx
65
66 # Add in symbols for the microcode registers
67 for num in range(16):
68 assembler.symbols["t%d" % num] = regIdx("NUM_INTREGS+%d" % num)
69 for num in range(8):
70 assembler.symbols["ufp%d" % num] = \
71 regIdx("FLOATREG_MICROFP(%d)" % num)
72 # Add in symbols for the segment descriptor registers
73 for letter in ("C", "D", "E", "F", "G", "H", "S"):
74 assembler.symbols["%ss" % letter.lower()] = \
75 regIdx("SEGMENT_REG_%sS" % letter)
76
77 # Add in symbols for the various checks of segment selectors.
78 for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck",
79 "SoftIntGateCheck", "SSCheck", "IretCheck", "IntCSCheck",
80 "TRCheck", "TSSCheck", "InGDTCheck", "LDTCheck"):
81 assembler.symbols[check] = "Seg%s" % check
82
83 for reg in ("TR", "IDTR"):
84 assembler.symbols[reg.lower()] = regIdx("SYS_SEGMENT_REG_%s" % reg)
85
86 for reg in ("TSL", "TSG"):
87 assembler.symbols[reg.lower()] = regIdx("SEGMENT_REG_%s" % reg)
88
89 # Miscellaneous symbols
90 symbols = {
91 "reg" : regIdx("env.reg"),
92 "xmml" : regIdx("FLOATREG_XMM_LOW(env.reg)"),
93 "xmmh" : regIdx("FLOATREG_XMM_HIGH(env.reg)"),
94 "regm" : regIdx("env.regm"),
95 "xmmlm" : regIdx("FLOATREG_XMM_LOW(env.regm)"),
96 "xmmhm" : regIdx("FLOATREG_XMM_HIGH(env.regm)"),
97 "mmx" : regIdx("FLOATREG_MMX(env.reg)"),
98 "mmxm" : regIdx("FLOATREG_MMX(env.regm)"),
99 "imm" : "adjustedImm",
100 "disp" : "adjustedDisp",
101 "seg" : regIdx("env.seg"),
102 "scale" : "env.scale",
103 "index" : regIdx("env.index"),
104 "base" : regIdx("env.base"),
105 "dsz" : "env.dataSize",
106 "asz" : "env.addressSize",
107 "ssz" : "env.stackSize"
108 }
109 assembler.symbols.update(symbols)
110
111 assembler.symbols["ldsz"] = \
112 "((env.dataSize == 8) ? 3 : (env.dataSize == 4) ? 2 : 1)"
113
114 assembler.symbols["lasz"] = \
115 "((env.addressSize == 8) ? 3 : (env.addressSize == 4) ? 2 : 1)"
116
117 assembler.symbols["lssz"] = \
118 "((env.stackSize == 8) ? 3 : (env.stackSize == 4) ? 2 : 1)"
119
120 # Short hand for common scale-index-base combinations.
121 assembler.symbols["sib"] = \
122 [symbols["scale"], symbols["index"], symbols["base"]]
123 assembler.symbols["riprel"] = \
124 ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
125
126 # This segment selects an internal address space mapped to MSRs,
127 # CPUID info, etc.
128 assembler.symbols["intseg"] = regIdx("SEGMENT_REG_MS")
129 # This segment always has base 0, and doesn't imply any special handling
130 # like the internal segment above
131 assembler.symbols["flatseg"] = regIdx("SEGMENT_REG_LS")
132
133 for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di', \
134 '8', '9', '10', '11', '12', '13', '14', '15'):
135 assembler.symbols["r%s" % reg] = \
136 regIdx("INTREG_R%s" % reg.upper())
137
138 for reg in ('ah', 'bh', 'ch', 'dh'):
139 assembler.symbols[reg] = \
140 regIdx("INTREG_FOLDED(INTREG_%s, IntFoldBit)" % reg.upper())
141
142 for reg in range(16):
143 assembler.symbols["cr%d" % reg] = regIdx("MISCREG_CR%d" % reg)
144
145 for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \
146 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'):
147 assembler.symbols[flag] = flag + "Bit"
148
149 for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
150 'MSTRZ', 'STRZ', 'MSTRC',
151 'OF', 'CF', 'ZF', 'CvZF',
152 'SF', 'PF', 'SxOF', 'SxOvZF'):
153 assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
154 assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
155 assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
156 assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
157
158 assembler.symbols["CTrue"] = "ConditionTests::True"
159 assembler.symbols["CFalse"] = "ConditionTests::False"
160
161 for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip',
162 'star', 'lstar', 'cstar', 'sf_mask',
163 'kernel_gs_base'):
164 assembler.symbols[reg] = regIdx("MISCREG_%s" % reg.upper())
165
166 for flag in ('Scalar', 'MultHi', 'Signed'):
167 assembler.symbols[flag] = 'Media%sOp' % flag
168
169 # Code literal which forces a default 64 bit operand size in 64 bit mode.
170 assembler.symbols["oszIn64Override"] = '''
171 if (machInst.mode.submode == SixtyFourBitMode &&
172 env.dataSize == 4)
173 env.dataSize = 8;
174 '''
175
176 assembler.symbols["maxOsz"] = '''
177 if (machInst.mode.submode == SixtyFourBitMode)
178 env.dataSize = 8;
179 else
180 env.dataSize = 4;
181 '''
182
183 def trimImm(width):
184 return "adjustedImm = adjustedImm & mask(%s);" % width
185
186 assembler.symbols["trimImm"] = trimImm
187
188 def labeler(labelStr):
189 return "label_%s" % labelStr
190
191 assembler.symbols["label"] = labeler
192
193 def rom_labeler(labelStr):
194 return "romMicroPC(RomLabels::extern_label_%s)" % labelStr
195
196 assembler.symbols["rom_label"] = rom_labeler
197
198 def rom_local_labeler(labelStr):
199 return "romMicroPC(RomLabels::label_%s)" % labelStr
200
201 assembler.symbols["rom_local_label"] = rom_local_labeler
202
203 def stack_index(index):
204 return regIdx("NUM_FLOATREGS + (((%s) + 8) %% 8)" % index)
205
206 assembler.symbols["st"] = stack_index
207 assembler.symbols["sti"] = stack_index("env.reg")
208 assembler.symbols["stim"] = stack_index("env.regm")
209
210 def readFpReg(reg_name):
211 return regIdx("MISCREG_%s" % reg_name)
212
213 assembler.symbols["fsw"] = readFpReg("FSW")
214 assembler.symbols["fcw"] = readFpReg("FCW")
|