1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// Redistribution and use of this software in source and binary forms,
7// with or without modification, are permitted provided that the
8// following conditions are met:
9//
10// The software must be used only for Non-Commercial Use which means any
11// use which is NOT directed to receiving any direct monetary
12// compensation for, or commercial advantage from such use. Illustrative
13// examples of non-commercial use are academic research, personal study,
14// teaching, education and corporate research & development.
15// Illustrative examples of commercial use are distributing products for
16// commercial advantage and providing services using the software for
17// commercial advantage.
18//
19// If you wish to use this software or functionality therein that may be
20// covered by patents for commercial use, please contact:
21// Director of Intellectual Property Licensing
22// Office of Strategy and Technology
23// Hewlett-Packard Company
24// 1501 Page Mill Road
25// Palo Alto, California 94304
26//
27// Redistributions of source code must retain the above copyright notice,
28// this list of conditions and the following disclaimer. Redistributions
29// in binary form must reproduce the above copyright notice, this list of
30// conditions and the following disclaimer in the documentation and/or
31// other materials provided with the distribution. Neither the name of
32// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
33// contributors may be used to endorse or promote products derived from
34// this software without specific prior written permission. No right of
35// sublicense is granted herewith. Derivatives of the software and
36// output created using the software may be prepared, but only for
37// Non-Commercial Uses. Derivatives of the software may be shared with
38// others provided: (i) the others agree to abide by the list of
39// conditions herein which includes the Non-Commercial Use restrictions;
40// and (ii) such Derivatives of the software include the above copyright
41// notice to acknowledge the contribution from this software where
42// applicable, this list of conditions and the disclaimer below.
43//
44// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
45// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
46// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
47// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
48// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
49// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
54// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55//
56// Authors: Gabe Black
57
58//Include the definitions of the micro ops.
59//These are python representations of static insts which stand on their own
60//and make up an internal instruction set. They are used by the micro
61//assembler.
62##include "microops/microops.isa"
63
64//Include code to build macroops in both C++ and python.
65##include "macroop.isa"
66
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// Redistribution and use of this software in source and binary forms,
7// with or without modification, are permitted provided that the
8// following conditions are met:
9//
10// The software must be used only for Non-Commercial Use which means any
11// use which is NOT directed to receiving any direct monetary
12// compensation for, or commercial advantage from such use. Illustrative
13// examples of non-commercial use are academic research, personal study,
14// teaching, education and corporate research & development.
15// Illustrative examples of commercial use are distributing products for
16// commercial advantage and providing services using the software for
17// commercial advantage.
18//
19// If you wish to use this software or functionality therein that may be
20// covered by patents for commercial use, please contact:
21// Director of Intellectual Property Licensing
22// Office of Strategy and Technology
23// Hewlett-Packard Company
24// 1501 Page Mill Road
25// Palo Alto, California 94304
26//
27// Redistributions of source code must retain the above copyright notice,
28// this list of conditions and the following disclaimer. Redistributions
29// in binary form must reproduce the above copyright notice, this list of
30// conditions and the following disclaimer in the documentation and/or
31// other materials provided with the distribution. Neither the name of
32// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
33// contributors may be used to endorse or promote products derived from
34// this software without specific prior written permission. No right of
35// sublicense is granted herewith. Derivatives of the software and
36// output created using the software may be prepared, but only for
37// Non-Commercial Uses. Derivatives of the software may be shared with
38// others provided: (i) the others agree to abide by the list of
39// conditions herein which includes the Non-Commercial Use restrictions;
40// and (ii) such Derivatives of the software include the above copyright
41// notice to acknowledge the contribution from this software where
42// applicable, this list of conditions and the disclaimer below.
43//
44// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
45// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
46// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
47// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
48// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
49// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
54// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55//
56// Authors: Gabe Black
57
58//Include the definitions of the micro ops.
59//These are python representations of static insts which stand on their own
60//and make up an internal instruction set. They are used by the micro
61//assembler.
62##include "microops/microops.isa"
63
64//Include code to build macroops in both C++ and python.
65##include "macroop.isa"
66
|
74 assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
75 # Add in symbols for the microcode registers
76 for num in range(15):
77 assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
78 for num in range(7):
79 assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num
80 # Add in symbols for the segment descriptor registers
81 for letter in ("C", "D", "E", "F", "G", "S"):
82 assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
83
84 # Add in symbols for the various checks of segment selectors.
85 for check in ("NoCheck", "CSCheck", "CallGateCheck",
86 "SSCheck", "IretCheck", "IntCSCheck"):
87 assembler.symbols[check] = "Seg%s" % check
88
89 for reg in ("TR", "IDTR"):
90 assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg
91
92 for reg in ("TSL", "TSG"):
93 assembler.symbols[reg.lower()] = "SEGMENT_REG_%s" % reg
94
95 # Miscellaneous symbols
96 symbols = {
97 "reg" : "env.reg",
98 "xmml" : "FLOATREG_XMM_LOW(env.reg)",
99 "xmmh" : "FLOATREG_XMM_HIGH(env.reg)",
100 "regm" : "env.regm",
101 "xmmlm" : "FLOATREG_XMM_LOW(env.regm)",
102 "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)",
103 "imm" : "adjustedImm",
104 "disp" : "adjustedDisp",
105 "seg" : "env.seg",
106 "scale" : "env.scale",
107 "index" : "env.index",
108 "base" : "env.base",
109 "dsz" : "env.dataSize",
110 "asz" : "env.addressSize",
111 "ssz" : "env.stackSize"
112 }
113 assembler.symbols.update(symbols)
114
115 assembler.symbols["ldsz"] = \
116 "((env.dataSize == 8) ? 3 : (env.dataSize == 4) ? 2 : 1)"
117
118 assembler.symbols["lasz"] = \
119 "((env.addressSize == 8) ? 3 : (env.addressSize == 4) ? 2 : 1)"
120
121 assembler.symbols["lssz"] = \
122 "((env.stackSize == 8) ? 3 : (env.stackSize == 4) ? 2 : 1)"
123
124 # Short hand for common scale-index-base combinations.
125 assembler.symbols["sib"] = \
126 [symbols["scale"], symbols["index"], symbols["base"]]
127 assembler.symbols["riprel"] = \
128 ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
129
130 # This segment selects an internal address space mapped to MSRs,
131 # CPUID info, etc.
132 assembler.symbols["intseg"] = "SEGMENT_REG_MS"
133 # This segment always has base 0, and doesn't imply any special handling
134 # like the internal segment above
135 assembler.symbols["flatseg"] = "SEGMENT_REG_LS"
136
137 for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
138 assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
139
140 for reg in range(15):
141 assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
142
143 for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \
144 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'):
145 assembler.symbols[flag] = flag + "Bit"
146
147 for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
148 'MSTRZ', 'STRZ', 'MSTRC',
149 'OF', 'CF', 'ZF', 'CvZF',
150 'SF', 'PF', 'SxOF', 'SxOvZF'):
151 assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
152 assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
153 assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
154 assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
155
156 assembler.symbols["CTrue"] = "ConditionTests::True"
157 assembler.symbols["CFalse"] = "ConditionTests::False"
158
159 # Code literal which forces a default 64 bit operand size in 64 bit mode.
160 assembler.symbols["oszIn64Override"] = '''
161 if (machInst.mode.submode == SixtyFourBitMode &&
162 env.dataSize == 4)
163 env.dataSize = 8;
164 '''
165
166 assembler.symbols["oszForPseudoDesc"] = '''
167 if (machInst.mode.submode == SixtyFourBitMode)
168 env.dataSize = 8;
169 else
170 env.dataSize = 4;
171 '''
172
173 def trimImm(width):
174 return "adjustedImm = adjustedImm & mask(%s);" % width
175
176 assembler.symbols["trimImm"] = trimImm
177
178 def labeler(labelStr):
179 return "label_%s" % labelStr
180
181 assembler.symbols["label"] = labeler
182
183 def stack_index(index):
184 return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index
185
186 assembler.symbols["st"] = stack_index
187
188 macroopDict = assembler.assemble(microcode)
| 77 assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
78 # Add in symbols for the microcode registers
79 for num in range(15):
80 assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
81 for num in range(7):
82 assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num
83 # Add in symbols for the segment descriptor registers
84 for letter in ("C", "D", "E", "F", "G", "S"):
85 assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
86
87 # Add in symbols for the various checks of segment selectors.
88 for check in ("NoCheck", "CSCheck", "CallGateCheck",
89 "SSCheck", "IretCheck", "IntCSCheck"):
90 assembler.symbols[check] = "Seg%s" % check
91
92 for reg in ("TR", "IDTR"):
93 assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg
94
95 for reg in ("TSL", "TSG"):
96 assembler.symbols[reg.lower()] = "SEGMENT_REG_%s" % reg
97
98 # Miscellaneous symbols
99 symbols = {
100 "reg" : "env.reg",
101 "xmml" : "FLOATREG_XMM_LOW(env.reg)",
102 "xmmh" : "FLOATREG_XMM_HIGH(env.reg)",
103 "regm" : "env.regm",
104 "xmmlm" : "FLOATREG_XMM_LOW(env.regm)",
105 "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)",
106 "imm" : "adjustedImm",
107 "disp" : "adjustedDisp",
108 "seg" : "env.seg",
109 "scale" : "env.scale",
110 "index" : "env.index",
111 "base" : "env.base",
112 "dsz" : "env.dataSize",
113 "asz" : "env.addressSize",
114 "ssz" : "env.stackSize"
115 }
116 assembler.symbols.update(symbols)
117
118 assembler.symbols["ldsz"] = \
119 "((env.dataSize == 8) ? 3 : (env.dataSize == 4) ? 2 : 1)"
120
121 assembler.symbols["lasz"] = \
122 "((env.addressSize == 8) ? 3 : (env.addressSize == 4) ? 2 : 1)"
123
124 assembler.symbols["lssz"] = \
125 "((env.stackSize == 8) ? 3 : (env.stackSize == 4) ? 2 : 1)"
126
127 # Short hand for common scale-index-base combinations.
128 assembler.symbols["sib"] = \
129 [symbols["scale"], symbols["index"], symbols["base"]]
130 assembler.symbols["riprel"] = \
131 ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
132
133 # This segment selects an internal address space mapped to MSRs,
134 # CPUID info, etc.
135 assembler.symbols["intseg"] = "SEGMENT_REG_MS"
136 # This segment always has base 0, and doesn't imply any special handling
137 # like the internal segment above
138 assembler.symbols["flatseg"] = "SEGMENT_REG_LS"
139
140 for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
141 assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
142
143 for reg in range(15):
144 assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
145
146 for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \
147 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'):
148 assembler.symbols[flag] = flag + "Bit"
149
150 for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
151 'MSTRZ', 'STRZ', 'MSTRC',
152 'OF', 'CF', 'ZF', 'CvZF',
153 'SF', 'PF', 'SxOF', 'SxOvZF'):
154 assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
155 assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
156 assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
157 assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
158
159 assembler.symbols["CTrue"] = "ConditionTests::True"
160 assembler.symbols["CFalse"] = "ConditionTests::False"
161
162 # Code literal which forces a default 64 bit operand size in 64 bit mode.
163 assembler.symbols["oszIn64Override"] = '''
164 if (machInst.mode.submode == SixtyFourBitMode &&
165 env.dataSize == 4)
166 env.dataSize = 8;
167 '''
168
169 assembler.symbols["oszForPseudoDesc"] = '''
170 if (machInst.mode.submode == SixtyFourBitMode)
171 env.dataSize = 8;
172 else
173 env.dataSize = 4;
174 '''
175
176 def trimImm(width):
177 return "adjustedImm = adjustedImm & mask(%s);" % width
178
179 assembler.symbols["trimImm"] = trimImm
180
181 def labeler(labelStr):
182 return "label_%s" % labelStr
183
184 assembler.symbols["label"] = labeler
185
186 def stack_index(index):
187 return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index
188
189 assembler.symbols["st"] = stack_index
190
191 macroopDict = assembler.assemble(microcode)
|