logical.py (7087:fb8d5786ff30) logical.py (8610:9bdd52a2214c)
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabe Black
37
38microcode = '''
39def macroop OR_R_R
40{
41 or reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
42};
43
44def macroop OR_M_I
45{
46 limm t2, imm
47 ldst t1, seg, sib, disp
48 or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
49 st t1, seg, sib, disp
50};
51
52def macroop OR_P_I
53{
54 limm t2, imm
55 rdip t7
56 ldst t1, seg, riprel, disp
57 or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
58 st t1, seg, riprel, disp
59};
60
61def macroop OR_LOCKED_M_I
62{
63 limm t2, imm
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabe Black
37
38microcode = '''
39def macroop OR_R_R
40{
41 or reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
42};
43
44def macroop OR_M_I
45{
46 limm t2, imm
47 ldst t1, seg, sib, disp
48 or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
49 st t1, seg, sib, disp
50};
51
52def macroop OR_P_I
53{
54 limm t2, imm
55 rdip t7
56 ldst t1, seg, riprel, disp
57 or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
58 st t1, seg, riprel, disp
59};
60
61def macroop OR_LOCKED_M_I
62{
63 limm t2, imm
64 mfence
64 ldstl t1, seg, sib, disp
65 or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
66 stul t1, seg, sib, disp
65 ldstl t1, seg, sib, disp
66 or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
67 stul t1, seg, sib, disp
68 mfence
67};
68
69def macroop OR_LOCKED_P_I
70{
71 limm t2, imm
72 rdip t7
69};
70
71def macroop OR_LOCKED_P_I
72{
73 limm t2, imm
74 rdip t7
75 mfence
73 ldstl t1, seg, riprel, disp
74 or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
75 stul t1, seg, riprel, disp
76 ldstl t1, seg, riprel, disp
77 or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
78 stul t1, seg, riprel, disp
79 mfence
76};
77
78def macroop OR_M_R
79{
80 ldst t1, seg, sib, disp
81 or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
82 st t1, seg, sib, disp
83};
84
85def macroop OR_P_R
86{
87 rdip t7
88 ldst t1, seg, riprel, disp
89 or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
90 st t1, seg, riprel, disp
91};
92
93def macroop OR_LOCKED_M_R
94{
80};
81
82def macroop OR_M_R
83{
84 ldst t1, seg, sib, disp
85 or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
86 st t1, seg, sib, disp
87};
88
89def macroop OR_P_R
90{
91 rdip t7
92 ldst t1, seg, riprel, disp
93 or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
94 st t1, seg, riprel, disp
95};
96
97def macroop OR_LOCKED_M_R
98{
99 mfence
95 ldstl t1, seg, sib, disp
96 or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
97 stul t1, seg, sib, disp
100 ldstl t1, seg, sib, disp
101 or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
102 stul t1, seg, sib, disp
103 mfence
98};
99
100def macroop OR_LOCKED_P_R
101{
102 rdip t7
104};
105
106def macroop OR_LOCKED_P_R
107{
108 rdip t7
109 mfence
103 ldstl t1, seg, riprel, disp
104 or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
105 stul t1, seg, riprel, disp
110 ldstl t1, seg, riprel, disp
111 or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
112 stul t1, seg, riprel, disp
113 mfence
106};
107
108def macroop OR_R_M
109{
110 ld t1, seg, sib, disp
111 or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
112};
113
114def macroop OR_R_P
115{
116 rdip t7
117 ld t1, seg, riprel, disp
118 or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
119};
120
121def macroop OR_R_I
122{
123 limm t1, imm
124 or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
125};
126
127def macroop XOR_R_R
128{
129 xor reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
130};
131
132def macroop XOR_R_I
133{
134 limm t1, imm
135 xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
136};
137
138def macroop XOR_M_I
139{
140 limm t2, imm
141 ldst t1, seg, sib, disp
142 xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
143 st t1, seg, sib, disp
144};
145
146def macroop XOR_P_I
147{
148 limm t2, imm
149 rdip t7
150 ldst t1, seg, riprel, disp
151 xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
152 st t1, seg, riprel, disp
153};
154
155def macroop XOR_LOCKED_M_I
156{
157 limm t2, imm
114};
115
116def macroop OR_R_M
117{
118 ld t1, seg, sib, disp
119 or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
120};
121
122def macroop OR_R_P
123{
124 rdip t7
125 ld t1, seg, riprel, disp
126 or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
127};
128
129def macroop OR_R_I
130{
131 limm t1, imm
132 or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
133};
134
135def macroop XOR_R_R
136{
137 xor reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
138};
139
140def macroop XOR_R_I
141{
142 limm t1, imm
143 xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
144};
145
146def macroop XOR_M_I
147{
148 limm t2, imm
149 ldst t1, seg, sib, disp
150 xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
151 st t1, seg, sib, disp
152};
153
154def macroop XOR_P_I
155{
156 limm t2, imm
157 rdip t7
158 ldst t1, seg, riprel, disp
159 xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
160 st t1, seg, riprel, disp
161};
162
163def macroop XOR_LOCKED_M_I
164{
165 limm t2, imm
166 mfence
158 ldstl t1, seg, sib, disp
159 xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
160 stul t1, seg, sib, disp
167 ldstl t1, seg, sib, disp
168 xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
169 stul t1, seg, sib, disp
170 mfence
161};
162
163def macroop XOR_LOCKED_P_I
164{
165 limm t2, imm
166 rdip t7
171};
172
173def macroop XOR_LOCKED_P_I
174{
175 limm t2, imm
176 rdip t7
177 mfence
167 ldstl t1, seg, riprel, disp
168 xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
169 stul t1, seg, riprel, disp
178 ldstl t1, seg, riprel, disp
179 xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
180 stul t1, seg, riprel, disp
181 mfence
170};
171
172def macroop XOR_M_R
173{
174 ldst t1, seg, sib, disp
175 xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
176 st t1, seg, sib, disp
177};
178
179def macroop XOR_P_R
180{
181 rdip t7
182 ldst t1, seg, riprel, disp
183 xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
184 st t1, seg, riprel, disp
185};
186
187def macroop XOR_LOCKED_M_R
188{
182};
183
184def macroop XOR_M_R
185{
186 ldst t1, seg, sib, disp
187 xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
188 st t1, seg, sib, disp
189};
190
191def macroop XOR_P_R
192{
193 rdip t7
194 ldst t1, seg, riprel, disp
195 xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
196 st t1, seg, riprel, disp
197};
198
199def macroop XOR_LOCKED_M_R
200{
201 mfence
189 ldstl t1, seg, sib, disp
190 xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
191 stul t1, seg, sib, disp
202 ldstl t1, seg, sib, disp
203 xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
204 stul t1, seg, sib, disp
205 mfence
192};
193
194def macroop XOR_LOCKED_P_R
195{
196 rdip t7
206};
207
208def macroop XOR_LOCKED_P_R
209{
210 rdip t7
211 mfence
197 ldstl t1, seg, riprel, disp
198 xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
199 stul t1, seg, riprel, disp
212 ldstl t1, seg, riprel, disp
213 xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
214 stul t1, seg, riprel, disp
215 mfence
200};
201
202def macroop XOR_R_M
203{
204 ld t1, seg, sib, disp
205 xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
206};
207
208def macroop XOR_R_P
209{
210 rdip t7
211 ld t1, seg, riprel, disp
212 xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
213};
214
215def macroop AND_R_R
216{
217 and reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
218};
219
220def macroop AND_R_M
221{
222 ld t1, seg, sib, disp
223 and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
224};
225
226def macroop AND_R_P
227{
228 rdip t7
229 ld t1, seg, riprel, disp
230 and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
231};
232
233def macroop AND_R_I
234{
235 limm t1, imm
236 and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
237};
238
239def macroop AND_M_I
240{
241 ldst t2, seg, sib, disp
242 limm t1, imm
243 and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
244 st t2, seg, sib, disp
245};
246
247def macroop AND_P_I
248{
249 rdip t7
250 ldst t2, seg, riprel, disp
251 limm t1, imm
252 and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
253 st t2, seg, riprel, disp
254};
255
256def macroop AND_LOCKED_M_I
257{
216};
217
218def macroop XOR_R_M
219{
220 ld t1, seg, sib, disp
221 xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
222};
223
224def macroop XOR_R_P
225{
226 rdip t7
227 ld t1, seg, riprel, disp
228 xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
229};
230
231def macroop AND_R_R
232{
233 and reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
234};
235
236def macroop AND_R_M
237{
238 ld t1, seg, sib, disp
239 and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
240};
241
242def macroop AND_R_P
243{
244 rdip t7
245 ld t1, seg, riprel, disp
246 and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
247};
248
249def macroop AND_R_I
250{
251 limm t1, imm
252 and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
253};
254
255def macroop AND_M_I
256{
257 ldst t2, seg, sib, disp
258 limm t1, imm
259 and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
260 st t2, seg, sib, disp
261};
262
263def macroop AND_P_I
264{
265 rdip t7
266 ldst t2, seg, riprel, disp
267 limm t1, imm
268 and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
269 st t2, seg, riprel, disp
270};
271
272def macroop AND_LOCKED_M_I
273{
274 mfence
258 ldstl t2, seg, sib, disp
259 limm t1, imm
260 and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
261 stul t2, seg, sib, disp
275 ldstl t2, seg, sib, disp
276 limm t1, imm
277 and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
278 stul t2, seg, sib, disp
279 mfence
262};
263
264def macroop AND_LOCKED_P_I
265{
266 rdip t7
280};
281
282def macroop AND_LOCKED_P_I
283{
284 rdip t7
285 mfence
267 ldstl t2, seg, riprel, disp
268 limm t1, imm
269 and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
270 stul t2, seg, riprel, disp
286 ldstl t2, seg, riprel, disp
287 limm t1, imm
288 and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
289 stul t2, seg, riprel, disp
290 mfence
271};
272
273def macroop AND_M_R
274{
275 ldst t1, seg, sib, disp
276 and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
277 st t1, seg, sib, disp
278};
279
280def macroop AND_P_R
281{
282 rdip t7
283 ldst t1, seg, riprel, disp
284 and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
285 st t1, seg, riprel, disp
286};
287
288def macroop AND_LOCKED_M_R
289{
291};
292
293def macroop AND_M_R
294{
295 ldst t1, seg, sib, disp
296 and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
297 st t1, seg, sib, disp
298};
299
300def macroop AND_P_R
301{
302 rdip t7
303 ldst t1, seg, riprel, disp
304 and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
305 st t1, seg, riprel, disp
306};
307
308def macroop AND_LOCKED_M_R
309{
310 mfence
290 ldstl t1, seg, sib, disp
291 and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
292 stul t1, seg, sib, disp
311 ldstl t1, seg, sib, disp
312 and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
313 stul t1, seg, sib, disp
314 mfence
293};
294
295def macroop AND_LOCKED_P_R
296{
297 rdip t7
315};
316
317def macroop AND_LOCKED_P_R
318{
319 rdip t7
320 mfence
298 ldstl t1, seg, riprel, disp
299 and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
300 stul t1, seg, riprel, disp
321 ldstl t1, seg, riprel, disp
322 and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
323 stul t1, seg, riprel, disp
324 mfence
301};
302
303def macroop NOT_R
304{
305 limm t1, -1
306 xor reg, reg, t1
307};
308
309def macroop NOT_M
310{
311 limm t1, -1
312 ldst t2, seg, sib, disp
313 xor t2, t2, t1
314 st t2, seg, sib, disp
315};
316
317def macroop NOT_P
318{
319 limm t1, -1
320 rdip t7
321 ldst t2, seg, riprel, disp
322 xor t2, t2, t1
323 st t2, seg, riprel, disp
324};
325
326def macroop NOT_LOCKED_M
327{
328 limm t1, -1
325};
326
327def macroop NOT_R
328{
329 limm t1, -1
330 xor reg, reg, t1
331};
332
333def macroop NOT_M
334{
335 limm t1, -1
336 ldst t2, seg, sib, disp
337 xor t2, t2, t1
338 st t2, seg, sib, disp
339};
340
341def macroop NOT_P
342{
343 limm t1, -1
344 rdip t7
345 ldst t2, seg, riprel, disp
346 xor t2, t2, t1
347 st t2, seg, riprel, disp
348};
349
350def macroop NOT_LOCKED_M
351{
352 limm t1, -1
353 mfence
329 ldstl t2, seg, sib, disp
330 xor t2, t2, t1
331 stul t2, seg, sib, disp
354 ldstl t2, seg, sib, disp
355 xor t2, t2, t1
356 stul t2, seg, sib, disp
357 mfence
332};
333
334def macroop NOT_LOCKED_P
335{
336 limm t1, -1
337 rdip t7
358};
359
360def macroop NOT_LOCKED_P
361{
362 limm t1, -1
363 rdip t7
364 mfence
338 ldstl t2, seg, riprel, disp
339 xor t2, t2, t1
340 stul t2, seg, riprel, disp
365 ldstl t2, seg, riprel, disp
366 xor t2, t2, t1
367 stul t2, seg, riprel, disp
368 mfence
341};
342'''
369};
370'''