1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_X86_INTMESSAGE_HH__
32#define __ARCH_X86_INTMESSAGE_HH__
33
34#include "arch/x86/x86_traits.hh"
35#include "base/bitunion.hh"
36#include "base/types.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "mem/request.hh"
40
41namespace X86ISA
42{
43 BitUnion32(TriggerIntMessage)
44 Bitfield<7, 0> destination;
45 Bitfield<15, 8> vector;
46 Bitfield<18, 16> deliveryMode;
47 Bitfield<19> destMode;
48 Bitfield<20> level;
49 Bitfield<21> trigger;
50 EndBitUnion(TriggerIntMessage)
51
52 namespace DeliveryMode
53 {
54 enum IntDeliveryMode {
55 Fixed = 0,
56 LowestPriority = 1,
57 SMI = 2,
58 NMI = 4,
59 INIT = 5,
60 SIPI = 6,
61 ExtInt = 7,
62 NumModes
63 };
64
65 static const char * const names[NumModes] = {
66 "Fixed", "LowestPriority", "SMI", "Reserved",
67 "NMI", "INIT", "Startup", "ExtInt"
68 };
69
70 static inline bool
71 isReserved(int mode)
72 {
73 return mode == 3;
74 }
75 }
76
77 static const Addr TriggerIntOffset = 0;
78
79 static inline PacketPtr
80 prepIntRequest(const uint8_t id, Addr offset, Addr size)
81 {
| 1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_X86_INTMESSAGE_HH__
32#define __ARCH_X86_INTMESSAGE_HH__
33
34#include "arch/x86/x86_traits.hh"
35#include "base/bitunion.hh"
36#include "base/types.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "mem/request.hh"
40
41namespace X86ISA
42{
43 BitUnion32(TriggerIntMessage)
44 Bitfield<7, 0> destination;
45 Bitfield<15, 8> vector;
46 Bitfield<18, 16> deliveryMode;
47 Bitfield<19> destMode;
48 Bitfield<20> level;
49 Bitfield<21> trigger;
50 EndBitUnion(TriggerIntMessage)
51
52 namespace DeliveryMode
53 {
54 enum IntDeliveryMode {
55 Fixed = 0,
56 LowestPriority = 1,
57 SMI = 2,
58 NMI = 4,
59 INIT = 5,
60 SIPI = 6,
61 ExtInt = 7,
62 NumModes
63 };
64
65 static const char * const names[NumModes] = {
66 "Fixed", "LowestPriority", "SMI", "Reserved",
67 "NMI", "INIT", "Startup", "ExtInt"
68 };
69
70 static inline bool
71 isReserved(int mode)
72 {
73 return mode == 3;
74 }
75 }
76
77 static const Addr TriggerIntOffset = 0;
78
79 static inline PacketPtr
80 prepIntRequest(const uint8_t id, Addr offset, Addr size)
81 {
|
85 PacketPtr pkt = new Packet(req, MemCmd::MessageReq);
86 pkt->allocate();
87 return pkt;
88 }
89
90 template<class T>
91 PacketPtr
92 buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
93 {
94 PacketPtr pkt = prepIntRequest(id, offset, size);
95 pkt->set<T>(payload);
96 return pkt;
97 }
98
99 static inline PacketPtr
100 buildIntRequest(const uint8_t id, TriggerIntMessage payload)
101 {
102 return buildIntRequest(id, payload, TriggerIntOffset,
103 sizeof(TriggerIntMessage));
104 }
105
106 static inline PacketPtr
107 buildIntResponse()
108 {
109 panic("buildIntResponse not implemented.\n");
110 }
111}
112
113#endif
| 87 PacketPtr pkt = new Packet(req, MemCmd::MessageReq);
88 pkt->allocate();
89 return pkt;
90 }
91
92 template<class T>
93 PacketPtr
94 buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
95 {
96 PacketPtr pkt = prepIntRequest(id, offset, size);
97 pkt->set<T>(payload);
98 return pkt;
99 }
100
101 static inline PacketPtr
102 buildIntRequest(const uint8_t id, TriggerIntMessage payload)
103 {
104 return buildIntRequest(id, payload, TriggerIntOffset,
105 sizeof(TriggerIntMessage));
106 }
107
108 static inline PacketPtr
109 buildIntResponse()
110 {
111 panic("buildIntResponse not implemented.\n");
112 }
113}
114
115#endif
|