1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_X86_INTMESSAGE_HH__
32#define __ARCH_X86_INTMESSAGE_HH__
33
34#include "arch/x86/x86_traits.hh"
35#include "base/bitunion.hh"
36#include "mem/packet.hh"
37#include "mem/request.hh"
38#include "sim/host.hh"
39
40namespace X86ISA
41{
42 BitUnion32(TriggerIntMessage)
43 Bitfield<7, 0> destination;
44 Bitfield<15, 8> vector;
45 Bitfield<18, 16> deliveryMode;
46 Bitfield<19> destMode;
| 1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_X86_INTMESSAGE_HH__
32#define __ARCH_X86_INTMESSAGE_HH__
33
34#include "arch/x86/x86_traits.hh"
35#include "base/bitunion.hh"
36#include "mem/packet.hh"
37#include "mem/request.hh"
38#include "sim/host.hh"
39
40namespace X86ISA
41{
42 BitUnion32(TriggerIntMessage)
43 Bitfield<7, 0> destination;
44 Bitfield<15, 8> vector;
45 Bitfield<18, 16> deliveryMode;
46 Bitfield<19> destMode;
|
| 47 Bitfield<20> level;
48 Bitfield<21> trigger;
|
47 EndBitUnion(TriggerIntMessage)
48
| 49 EndBitUnion(TriggerIntMessage)
50
|
| 51 namespace DeliveryMode
52 {
53 enum IntDeliveryMode {
54 Fixed = 0,
55 LowestPriority = 1,
56 SMI = 2,
57 NMI = 4,
58 INIT = 5,
59 ExtInt = 7,
60 NumModes
61 };
62
63 static const char * const names[NumModes] = {
64 "Fixed", "LowestPriority", "SMI", "Reserved",
65 "NMI", "INIT", "Reserved", "ExtInt"
66 };
67
68 static inline bool
69 isUnmaskable(int mode)
70 {
71 return (mode == SMI || mode == NMI ||
72 mode == INIT || mode == ExtInt);
73 }
74
75 static inline bool
76 isMaskable(int mode)
77 {
78 return (mode == Fixed || mode == LowestPriority);
79 }
80
81 static inline bool
82 isReserved(int mode)
83 {
84 return !(isMaskable(mode) || isUnmaskable(mode));
85 }
86 }
87
|
49 static const Addr TriggerIntOffset = 0;
50
51 static inline PacketPtr
52 prepIntRequest(const uint8_t id, Addr offset, Addr size)
53 {
54 RequestPtr req = new Request(x86InterruptAddress(id, offset),
55 size, UNCACHEABLE);
56 PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast);
57 pkt->allocate();
58 return pkt;
59 }
60
61 template<class T>
62 PacketPtr
63 buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
64 {
65 PacketPtr pkt = prepIntRequest(id, offset, size);
66 pkt->set<T>(payload);
67 return pkt;
68 }
69
70 static inline PacketPtr
71 buildIntRequest(const uint8_t id, TriggerIntMessage payload)
72 {
73 return buildIntRequest(id, payload, TriggerIntOffset,
74 sizeof(TriggerIntMessage));
75 }
76
77 static inline PacketPtr
78 buildIntResponse()
79 {
80 panic("buildIntResponse not implemented.\n");
81 }
82}
83
84#endif
| 88 static const Addr TriggerIntOffset = 0;
89
90 static inline PacketPtr
91 prepIntRequest(const uint8_t id, Addr offset, Addr size)
92 {
93 RequestPtr req = new Request(x86InterruptAddress(id, offset),
94 size, UNCACHEABLE);
95 PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast);
96 pkt->allocate();
97 return pkt;
98 }
99
100 template<class T>
101 PacketPtr
102 buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
103 {
104 PacketPtr pkt = prepIntRequest(id, offset, size);
105 pkt->set<T>(payload);
106 return pkt;
107 }
108
109 static inline PacketPtr
110 buildIntRequest(const uint8_t id, TriggerIntMessage payload)
111 {
112 return buildIntRequest(id, payload, TriggerIntOffset,
113 sizeof(TriggerIntMessage));
114 }
115
116 static inline PacketPtr
117 buildIntResponse()
118 {
119 panic("buildIntResponse not implemented.\n");
120 }
121}
122
123#endif
|