1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#include "arch/x86/insts/static_inst.hh"
42
43#include "arch/x86/regs/segment.hh"
44#include "cpu/reg_class.hh"
45
46namespace X86ISA
47{
48 void X86StaticInst::printMnemonic(std::ostream &os,
49 const char * mnemonic) const
50 {
51 ccprintf(os, " %s ", mnemonic);
52 }
53
54 void X86StaticInst::printMnemonic(std::ostream &os,
55 const char * instMnemonic, const char * mnemonic) const
56 {
57 ccprintf(os, " %s : %s ", instMnemonic, mnemonic);
58 }
59
60 void X86StaticInst::printSegment(std::ostream &os, int segment) const
61 {
62 switch (segment)
63 {
64 case SEGMENT_REG_ES:
65 ccprintf(os, "ES");
66 break;
67 case SEGMENT_REG_CS:
68 ccprintf(os, "CS");
69 break;
70 case SEGMENT_REG_SS:
71 ccprintf(os, "SS");
72 break;
73 case SEGMENT_REG_DS:
74 ccprintf(os, "DS");
75 break;
76 case SEGMENT_REG_FS:
77 ccprintf(os, "FS");
78 break;
79 case SEGMENT_REG_GS:
80 ccprintf(os, "GS");
81 break;
82 case SEGMENT_REG_HS:
83 ccprintf(os, "HS");
84 break;
85 case SEGMENT_REG_TSL:
86 ccprintf(os, "TSL");
87 break;
88 case SEGMENT_REG_TSG:
89 ccprintf(os, "TSG");
90 break;
91 case SEGMENT_REG_LS:
92 ccprintf(os, "LS");
93 break;
94 case SEGMENT_REG_MS:
95 ccprintf(os, "MS");
96 break;
97 case SYS_SEGMENT_REG_TR:
98 ccprintf(os, "TR");
99 break;
100 case SYS_SEGMENT_REG_IDTR:
101 ccprintf(os, "IDTR");
102 break;
103 default:
104 panic("Unrecognized segment %d\n", segment);
105 }
106 }
107
108 void
109 X86StaticInst::printSrcReg(std::ostream &os, int reg, int size) const
110 {
111 if (_numSrcRegs > reg)
112 printReg(os, _srcRegIdx[reg], size);
113 }
114
115 void
116 X86StaticInst::printDestReg(std::ostream &os, int reg, int size) const
117 {
118 if (_numDestRegs > reg)
119 printReg(os, _destRegIdx[reg], size);
120 }
121
122 void
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#include "arch/x86/insts/static_inst.hh"
42
43#include "arch/x86/regs/segment.hh"
44#include "cpu/reg_class.hh"
45
46namespace X86ISA
47{
48 void X86StaticInst::printMnemonic(std::ostream &os,
49 const char * mnemonic) const
50 {
51 ccprintf(os, " %s ", mnemonic);
52 }
53
54 void X86StaticInst::printMnemonic(std::ostream &os,
55 const char * instMnemonic, const char * mnemonic) const
56 {
57 ccprintf(os, " %s : %s ", instMnemonic, mnemonic);
58 }
59
60 void X86StaticInst::printSegment(std::ostream &os, int segment) const
61 {
62 switch (segment)
63 {
64 case SEGMENT_REG_ES:
65 ccprintf(os, "ES");
66 break;
67 case SEGMENT_REG_CS:
68 ccprintf(os, "CS");
69 break;
70 case SEGMENT_REG_SS:
71 ccprintf(os, "SS");
72 break;
73 case SEGMENT_REG_DS:
74 ccprintf(os, "DS");
75 break;
76 case SEGMENT_REG_FS:
77 ccprintf(os, "FS");
78 break;
79 case SEGMENT_REG_GS:
80 ccprintf(os, "GS");
81 break;
82 case SEGMENT_REG_HS:
83 ccprintf(os, "HS");
84 break;
85 case SEGMENT_REG_TSL:
86 ccprintf(os, "TSL");
87 break;
88 case SEGMENT_REG_TSG:
89 ccprintf(os, "TSG");
90 break;
91 case SEGMENT_REG_LS:
92 ccprintf(os, "LS");
93 break;
94 case SEGMENT_REG_MS:
95 ccprintf(os, "MS");
96 break;
97 case SYS_SEGMENT_REG_TR:
98 ccprintf(os, "TR");
99 break;
100 case SYS_SEGMENT_REG_IDTR:
101 ccprintf(os, "IDTR");
102 break;
103 default:
104 panic("Unrecognized segment %d\n", segment);
105 }
106 }
107
108 void
109 X86StaticInst::printSrcReg(std::ostream &os, int reg, int size) const
110 {
111 if (_numSrcRegs > reg)
112 printReg(os, _srcRegIdx[reg], size);
113 }
114
115 void
116 X86StaticInst::printDestReg(std::ostream &os, int reg, int size) const
117 {
118 if (_numDestRegs > reg)
119 printReg(os, _destRegIdx[reg], size);
120 }
121
122 void
|
123 X86StaticInst::printReg(std::ostream &os, int reg, int size) const
| 123 X86StaticInst::printReg(std::ostream &os, RegId reg, int size) const
|
124 {
125 assert(size == 1 || size == 2 || size == 4 || size == 8);
126 static const char * abcdFormats[9] =
127 {"", "%s", "%sx", "", "e%sx", "", "", "", "r%sx"};
128 static const char * piFormats[9] =
129 {"", "%s", "%s", "", "e%s", "", "", "", "r%s"};
130 static const char * longFormats[9] =
131 {"", "r%sb", "r%sw", "", "r%sd", "", "", "", "r%s"};
132 static const char * microFormats[9] =
133 {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
134
| 124 {
125 assert(size == 1 || size == 2 || size == 4 || size == 8);
126 static const char * abcdFormats[9] =
127 {"", "%s", "%sx", "", "e%sx", "", "", "", "r%sx"};
128 static const char * piFormats[9] =
129 {"", "%s", "%s", "", "e%s", "", "", "", "r%s"};
130 static const char * longFormats[9] =
131 {"", "r%sb", "r%sw", "", "r%sd", "", "", "", "r%s"};
132 static const char * microFormats[9] =
133 {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
134
|
135 RegIndex rel_reg;
| 135 RegIndex reg_idx = reg.regIdx;
|
136
| 136
|
137 switch (regIdxToClass(reg, &rel_reg)) {
| 137 switch (reg.regClass) {
|
138 case IntRegClass: {
139 const char * suffix = "";
| 138 case IntRegClass: {
139 const char * suffix = "";
|
140 bool fold = rel_reg & IntFoldBit;
141 rel_reg &= ~IntFoldBit;
| 140 bool fold = reg_idx & IntFoldBit;
141 reg_idx &= ~IntFoldBit;
|
142
143 if (fold)
144 suffix = "h";
| 142
143 if (fold)
144 suffix = "h";
|
145 else if (rel_reg < 8 && size == 1)
| 145 else if (reg_idx < 8 && size == 1)
|
146 suffix = "l";
147
| 146 suffix = "l";
147
|
148 switch (rel_reg) {
| 148 switch (reg_idx) {
|
149 case INTREG_RAX:
150 ccprintf(os, abcdFormats[size], "a");
151 break;
152 case INTREG_RBX:
153 ccprintf(os, abcdFormats[size], "b");
154 break;
155 case INTREG_RCX:
156 ccprintf(os, abcdFormats[size], "c");
157 break;
158 case INTREG_RDX:
159 ccprintf(os, abcdFormats[size], "d");
160 break;
161 case INTREG_RSP:
162 ccprintf(os, piFormats[size], "sp");
163 break;
164 case INTREG_RBP:
165 ccprintf(os, piFormats[size], "bp");
166 break;
167 case INTREG_RSI:
168 ccprintf(os, piFormats[size], "si");
169 break;
170 case INTREG_RDI:
171 ccprintf(os, piFormats[size], "di");
172 break;
173 case INTREG_R8W:
174 ccprintf(os, longFormats[size], "8");
175 break;
176 case INTREG_R9W:
177 ccprintf(os, longFormats[size], "9");
178 break;
179 case INTREG_R10W:
180 ccprintf(os, longFormats[size], "10");
181 break;
182 case INTREG_R11W:
183 ccprintf(os, longFormats[size], "11");
184 break;
185 case INTREG_R12W:
186 ccprintf(os, longFormats[size], "12");
187 break;
188 case INTREG_R13W:
189 ccprintf(os, longFormats[size], "13");
190 break;
191 case INTREG_R14W:
192 ccprintf(os, longFormats[size], "14");
193 break;
194 case INTREG_R15W:
195 ccprintf(os, longFormats[size], "15");
196 break;
197 default:
| 149 case INTREG_RAX:
150 ccprintf(os, abcdFormats[size], "a");
151 break;
152 case INTREG_RBX:
153 ccprintf(os, abcdFormats[size], "b");
154 break;
155 case INTREG_RCX:
156 ccprintf(os, abcdFormats[size], "c");
157 break;
158 case INTREG_RDX:
159 ccprintf(os, abcdFormats[size], "d");
160 break;
161 case INTREG_RSP:
162 ccprintf(os, piFormats[size], "sp");
163 break;
164 case INTREG_RBP:
165 ccprintf(os, piFormats[size], "bp");
166 break;
167 case INTREG_RSI:
168 ccprintf(os, piFormats[size], "si");
169 break;
170 case INTREG_RDI:
171 ccprintf(os, piFormats[size], "di");
172 break;
173 case INTREG_R8W:
174 ccprintf(os, longFormats[size], "8");
175 break;
176 case INTREG_R9W:
177 ccprintf(os, longFormats[size], "9");
178 break;
179 case INTREG_R10W:
180 ccprintf(os, longFormats[size], "10");
181 break;
182 case INTREG_R11W:
183 ccprintf(os, longFormats[size], "11");
184 break;
185 case INTREG_R12W:
186 ccprintf(os, longFormats[size], "12");
187 break;
188 case INTREG_R13W:
189 ccprintf(os, longFormats[size], "13");
190 break;
191 case INTREG_R14W:
192 ccprintf(os, longFormats[size], "14");
193 break;
194 case INTREG_R15W:
195 ccprintf(os, longFormats[size], "15");
196 break;
197 default:
|
198 ccprintf(os, microFormats[size], rel_reg - NUM_INTREGS);
| 198 ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS);
|
199 }
200 ccprintf(os, suffix);
201 break;
202 }
203
204 case FloatRegClass: {
| 199 }
200 ccprintf(os, suffix);
201 break;
202 }
203
204 case FloatRegClass: {
|
205 if (rel_reg < NumMMXRegs) {
206 ccprintf(os, "%%mmx%d", rel_reg);
| 205 if (reg_idx < NumMMXRegs) {
206 ccprintf(os, "%%mmx%d", reg_idx);
|
207 return;
208 }
| 207 return;
208 }
|
209 rel_reg -= NumMMXRegs;
210 if (rel_reg < NumXMMRegs * 2) {
211 ccprintf(os, "%%xmm%d_%s", rel_reg / 2,
212 (rel_reg % 2) ? "high": "low");
| 209 reg_idx -= NumMMXRegs;
210 if (reg_idx < NumXMMRegs * 2) {
211 ccprintf(os, "%%xmm%d_%s", reg_idx / 2,
212 (reg_idx % 2) ? "high": "low");
|
213 return;
214 }
| 213 return;
214 }
|
215 rel_reg -= NumXMMRegs * 2;
216 if (rel_reg < NumMicroFpRegs) {
217 ccprintf(os, "%%ufp%d", rel_reg);
| 215 reg_idx -= NumXMMRegs * 2;
216 if (reg_idx < NumMicroFpRegs) {
217 ccprintf(os, "%%ufp%d", reg_idx);
|
218 return;
219 }
| 218 return;
219 }
|
220 rel_reg -= NumMicroFpRegs;
221 ccprintf(os, "%%st(%d)", rel_reg);
| 220 reg_idx -= NumMicroFpRegs;
221 ccprintf(os, "%%st(%d)", reg_idx);
|
222 break;
223 }
224
225 case CCRegClass:
| 222 break;
223 }
224
225 case CCRegClass:
|
226 ccprintf(os, "%%cc%d", rel_reg);
| 226 ccprintf(os, "%%cc%d", reg_idx);
|
227 break;
228
229 case MiscRegClass:
| 227 break;
228
229 case MiscRegClass:
|
230 switch (rel_reg) {
| 230 switch (reg_idx) {
|
231 default:
| 231 default:
|
232 ccprintf(os, "%%ctrl%d", rel_reg);
| 232 ccprintf(os, "%%ctrl%d", reg_idx);
|
233 }
234 break;
235 }
236 }
237
238 void X86StaticInst::printMem(std::ostream &os, uint8_t segment,
239 uint8_t scale, RegIndex index, RegIndex base,
240 uint64_t disp, uint8_t addressSize, bool rip) const
241 {
242 bool someAddr = false;
243 printSegment(os, segment);
244 os << ":[";
245 if (rip) {
246 os << "rip";
247 someAddr = true;
248 } else {
249 if (scale != 0 && index != ZeroReg)
250 {
251 if (scale != 1)
252 ccprintf(os, "%d*", scale);
| 233 }
234 break;
235 }
236 }
237
238 void X86StaticInst::printMem(std::ostream &os, uint8_t segment,
239 uint8_t scale, RegIndex index, RegIndex base,
240 uint64_t disp, uint8_t addressSize, bool rip) const
241 {
242 bool someAddr = false;
243 printSegment(os, segment);
244 os << ":[";
245 if (rip) {
246 os << "rip";
247 someAddr = true;
248 } else {
249 if (scale != 0 && index != ZeroReg)
250 {
251 if (scale != 1)
252 ccprintf(os, "%d*", scale);
|
253 printReg(os, index, addressSize);
| 253 printReg(os, InstRegIndex(index), addressSize);
|
254 someAddr = true;
255 }
256 if (base != ZeroReg)
257 {
258 if (someAddr)
259 os << " + ";
| 254 someAddr = true;
255 }
256 if (base != ZeroReg)
257 {
258 if (someAddr)
259 os << " + ";
|
260 printReg(os, base, addressSize);
| 260 printReg(os, InstRegIndex(base), addressSize);
|
261 someAddr = true;
262 }
263 }
264 if (disp != 0)
265 {
266 if (someAddr)
267 os << " + ";
268 ccprintf(os, "%#x", disp);
269 someAddr = true;
270 }
271 if (!someAddr)
272 os << "0";
273 os << "]";
274 }
275
276 std::string X86StaticInst::generateDisassembly(Addr pc,
277 const SymbolTable *symtab) const
278 {
279 std::stringstream ss;
280
281 printMnemonic(ss, mnemonic);
282
283 return ss.str();
284 }
285}
| 261 someAddr = true;
262 }
263 }
264 if (disp != 0)
265 {
266 if (someAddr)
267 os << " + ";
268 ccprintf(os, "%#x", disp);
269 someAddr = true;
270 }
271 if (!someAddr)
272 os << "0";
273 os << "]";
274 }
275
276 std::string X86StaticInst::generateDisassembly(Addr pc,
277 const SymbolTable *symtab) const
278 {
279 std::stringstream ss;
280
281 printMnemonic(ss, mnemonic);
282
283 return ss.str();
284 }
285}
|