1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_FAULTS_HH__
41#define __ARCH_X86_FAULTS_HH__
42
43#include "base/bitunion.hh"
44#include "base/misc.hh"
45#include "sim/faults.hh"
46#include "sim/tlb.hh"
47
48#include <string>
49
50namespace X86ISA
51{
52 // Base class for all x86 "faults" where faults is in the m5 sense
53 class X86FaultBase : public FaultBase
54 {
55 protected:
56 const char * faultName;
57 const char * mnem;
58 uint8_t vector;
59 uint64_t errorCode;
60
61 X86FaultBase(const char * _faultName, const char * _mnem,
62 const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
63 : faultName(_faultName), mnem(_mnem),
64 vector(_vector), errorCode(_errorCode)
65 {
66 }
67
68 const char * name() const
69 {
70 return faultName;
71 }
72
73 virtual bool isBenign()
74 {
75 return true;
76 }
77
78 virtual const char * mnemonic() const
79 {
80 return mnem;
81 }
82
83 virtual bool isSoft()
84 {
85 return false;
86 }
87
88#if FULL_SYSTEM
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_FAULTS_HH__
41#define __ARCH_X86_FAULTS_HH__
42
43#include "base/bitunion.hh"
44#include "base/misc.hh"
45#include "sim/faults.hh"
46#include "sim/tlb.hh"
47
48#include <string>
49
50namespace X86ISA
51{
52 // Base class for all x86 "faults" where faults is in the m5 sense
53 class X86FaultBase : public FaultBase
54 {
55 protected:
56 const char * faultName;
57 const char * mnem;
58 uint8_t vector;
59 uint64_t errorCode;
60
61 X86FaultBase(const char * _faultName, const char * _mnem,
62 const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
63 : faultName(_faultName), mnem(_mnem),
64 vector(_vector), errorCode(_errorCode)
65 {
66 }
67
68 const char * name() const
69 {
70 return faultName;
71 }
72
73 virtual bool isBenign()
74 {
75 return true;
76 }
77
78 virtual const char * mnemonic() const
79 {
80 return mnem;
81 }
82
83 virtual bool isSoft()
84 {
85 return false;
86 }
87
88#if FULL_SYSTEM
|
89 void invoke(ThreadContext * tc);
| 89 void invoke(ThreadContext * tc,
90 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
90
91 virtual std::string describe() const;
92#endif
93 };
94
95 // Base class for x86 faults which behave as if the underlying instruction
96 // didn't happen.
97 class X86Fault : public X86FaultBase
98 {
99 protected:
100 X86Fault(const char * name, const char * mnem,
101 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
102 : X86FaultBase(name, mnem, vector, _errorCode)
103 {}
104 };
105
106 // Base class for x86 traps which behave as if the underlying instruction
107 // completed.
108 class X86Trap : public X86FaultBase
109 {
110 protected:
111 X86Trap(const char * name, const char * mnem,
112 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
113 : X86FaultBase(name, mnem, vector, _errorCode)
114 {}
115
116#if FULL_SYSTEM
| 91
92 virtual std::string describe() const;
93#endif
94 };
95
96 // Base class for x86 faults which behave as if the underlying instruction
97 // didn't happen.
98 class X86Fault : public X86FaultBase
99 {
100 protected:
101 X86Fault(const char * name, const char * mnem,
102 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
103 : X86FaultBase(name, mnem, vector, _errorCode)
104 {}
105 };
106
107 // Base class for x86 traps which behave as if the underlying instruction
108 // completed.
109 class X86Trap : public X86FaultBase
110 {
111 protected:
112 X86Trap(const char * name, const char * mnem,
113 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
114 : X86FaultBase(name, mnem, vector, _errorCode)
115 {}
116
117#if FULL_SYSTEM
|
117 void invoke(ThreadContext * tc);
| 118 void invoke(ThreadContext * tc,
119 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
118#endif
119 };
120
121 // Base class for x86 aborts which seem to be catastrophic failures.
122 class X86Abort : public X86FaultBase
123 {
124 protected:
125 X86Abort(const char * name, const char * mnem,
126 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
127 : X86FaultBase(name, mnem, vector, _errorCode)
128 {}
129
130#if FULL_SYSTEM
| 120#endif
121 };
122
123 // Base class for x86 aborts which seem to be catastrophic failures.
124 class X86Abort : public X86FaultBase
125 {
126 protected:
127 X86Abort(const char * name, const char * mnem,
128 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
129 : X86FaultBase(name, mnem, vector, _errorCode)
130 {}
131
132#if FULL_SYSTEM
|
131 void invoke(ThreadContext * tc);
| 133 void invoke(ThreadContext * tc,
134 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
132#endif
133 };
134
135 // Base class for x86 interrupts.
136 class X86Interrupt : public X86FaultBase
137 {
138 protected:
139 X86Interrupt(const char * name, const char * mnem,
140 const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
141 : X86FaultBase(name, mnem, _vector, _errorCode)
142 {}
143 };
144
145 class UnimpInstFault : public FaultBase
146 {
147 public:
148 const char * name() const
149 {
150 return "unimplemented_micro";
151 }
152
| 135#endif
136 };
137
138 // Base class for x86 interrupts.
139 class X86Interrupt : public X86FaultBase
140 {
141 protected:
142 X86Interrupt(const char * name, const char * mnem,
143 const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
144 : X86FaultBase(name, mnem, _vector, _errorCode)
145 {}
146 };
147
148 class UnimpInstFault : public FaultBase
149 {
150 public:
151 const char * name() const
152 {
153 return "unimplemented_micro";
154 }
155
|
153 void invoke(ThreadContext * tc)
| 156 void invoke(ThreadContext * tc,
157 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
|
154 {
155 panic("Unimplemented instruction!");
156 }
157 };
158
159 static inline Fault genMachineCheckFault()
160 {
161 panic("Machine check fault not implemented in x86!\n");
162 }
163
164 // Below is a summary of the interrupt/exception information in the
165 // architecture manuals.
166
167 // Class | Type | vector | Cause | mnem
168 //------------------------------------------------------------------------
169 //Contrib Fault 0 Divide-by-Zero-Error #DE
170 //Benign Either 1 Debug #DB
171 //Benign Interrupt 2 Non-Maskable-Interrupt #NMI
172 //Benign Trap 3 Breakpoint #BP
173 //Benign Trap 4 Overflow #OF
174 //Benign Fault 5 Bound-Range #BR
175 //Benign Fault 6 Invalid-Opcode #UD
176 //Benign Fault 7 Device-Not-Available #NM
177 //Benign Abort 8 Double-Fault #DF
178 // 9 Coprocessor-Segment-Overrun
179 //Contrib Fault 10 Invalid-TSS #TS
180 //Contrib Fault 11 Segment-Not-Present #NP
181 //Contrib Fault 12 Stack #SS
182 //Contrib Fault 13 General-Protection #GP
183 //Either Fault 14 Page-Fault #PF
184 // 15 Reserved
185 //Benign Fault 16 x87 Floating-Point Exception Pending #MF
186 //Benign Fault 17 Alignment-Check #AC
187 //Benign Abort 18 Machine-Check #MC
188 //Benign Fault 19 SIMD Floating-Point #XF
189 // 20-29 Reserved
190 //Contrib ? 30 Security Exception #SX
191 // 31 Reserved
192 //Benign Interrupt 0-255 External Interrupts #INTR
193 //Benign Interrupt 0-255 Software Interrupts INTn
194
195 class DivideByZero : public X86Fault
196 {
197 public:
198 DivideByZero() :
199 X86Fault("Divide-by-Zero-Error", "#DE", 0)
200 {}
201 };
202
203 class DebugException : public X86FaultBase
204 {
205 public:
206 DebugException() :
207 X86FaultBase("Debug", "#DB", 1)
208 {}
209 };
210
211 class NonMaskableInterrupt : public X86Interrupt
212 {
213 public:
214 NonMaskableInterrupt(uint8_t _vector) :
215 X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
216 {}
217 };
218
219 class Breakpoint : public X86Trap
220 {
221 public:
222 Breakpoint() :
223 X86Trap("Breakpoint", "#BP", 3)
224 {}
225 };
226
227 class OverflowTrap : public X86Trap
228 {
229 public:
230 OverflowTrap() :
231 X86Trap("Overflow", "#OF", 4)
232 {}
233 };
234
235 class BoundRange : public X86Fault
236 {
237 public:
238 BoundRange() :
239 X86Fault("Bound-Range", "#BR", 5)
240 {}
241 };
242
243 class InvalidOpcode : public X86Fault
244 {
245 public:
246 InvalidOpcode() :
247 X86Fault("Invalid-Opcode", "#UD", 6)
248 {}
249 };
250
251 class DeviceNotAvailable : public X86Fault
252 {
253 public:
254 DeviceNotAvailable() :
255 X86Fault("Device-Not-Available", "#NM", 7)
256 {}
257 };
258
259 class DoubleFault : public X86Abort
260 {
261 public:
262 DoubleFault() :
263 X86Abort("Double-Fault", "#DF", 8, 0)
264 {}
265 };
266
267 class InvalidTSS : public X86Fault
268 {
269 public:
270 InvalidTSS(uint32_t _errorCode) :
271 X86Fault("Invalid-TSS", "#TS", 10, _errorCode)
272 {}
273 };
274
275 class SegmentNotPresent : public X86Fault
276 {
277 public:
278 SegmentNotPresent(uint32_t _errorCode) :
279 X86Fault("Segment-Not-Present", "#NP", 11, _errorCode)
280 {}
281 };
282
283 class StackFault : public X86Fault
284 {
285 public:
286 StackFault(uint32_t _errorCode) :
287 X86Fault("Stack", "#SS", 12, _errorCode)
288 {}
289 };
290
291 class GeneralProtection : public X86Fault
292 {
293 public:
294 GeneralProtection(uint32_t _errorCode) :
295 X86Fault("General-Protection", "#GP", 13, _errorCode)
296 {}
297 };
298
299 class PageFault : public X86Fault
300 {
301 protected:
302 BitUnion32(PageFaultErrorCode)
303 Bitfield<0> present;
304 Bitfield<1> write;
305 Bitfield<2> user;
306 Bitfield<3> reserved;
307 Bitfield<4> fetch;
308 EndBitUnion(PageFaultErrorCode)
309
310 Addr addr;
311
312 public:
313 PageFault(Addr _addr, uint32_t _errorCode) :
314 X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
315 {}
316
317 PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
318 bool user, bool reserved) :
319 X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
320 {
321 PageFaultErrorCode code = 0;
322 code.present = present;
323 code.write = (mode == BaseTLB::Write);
324 code.user = user;
325 code.reserved = reserved;
326 code.fetch = (mode == BaseTLB::Execute);
327 errorCode = code;
328 }
329
| 158 {
159 panic("Unimplemented instruction!");
160 }
161 };
162
163 static inline Fault genMachineCheckFault()
164 {
165 panic("Machine check fault not implemented in x86!\n");
166 }
167
168 // Below is a summary of the interrupt/exception information in the
169 // architecture manuals.
170
171 // Class | Type | vector | Cause | mnem
172 //------------------------------------------------------------------------
173 //Contrib Fault 0 Divide-by-Zero-Error #DE
174 //Benign Either 1 Debug #DB
175 //Benign Interrupt 2 Non-Maskable-Interrupt #NMI
176 //Benign Trap 3 Breakpoint #BP
177 //Benign Trap 4 Overflow #OF
178 //Benign Fault 5 Bound-Range #BR
179 //Benign Fault 6 Invalid-Opcode #UD
180 //Benign Fault 7 Device-Not-Available #NM
181 //Benign Abort 8 Double-Fault #DF
182 // 9 Coprocessor-Segment-Overrun
183 //Contrib Fault 10 Invalid-TSS #TS
184 //Contrib Fault 11 Segment-Not-Present #NP
185 //Contrib Fault 12 Stack #SS
186 //Contrib Fault 13 General-Protection #GP
187 //Either Fault 14 Page-Fault #PF
188 // 15 Reserved
189 //Benign Fault 16 x87 Floating-Point Exception Pending #MF
190 //Benign Fault 17 Alignment-Check #AC
191 //Benign Abort 18 Machine-Check #MC
192 //Benign Fault 19 SIMD Floating-Point #XF
193 // 20-29 Reserved
194 //Contrib ? 30 Security Exception #SX
195 // 31 Reserved
196 //Benign Interrupt 0-255 External Interrupts #INTR
197 //Benign Interrupt 0-255 Software Interrupts INTn
198
199 class DivideByZero : public X86Fault
200 {
201 public:
202 DivideByZero() :
203 X86Fault("Divide-by-Zero-Error", "#DE", 0)
204 {}
205 };
206
207 class DebugException : public X86FaultBase
208 {
209 public:
210 DebugException() :
211 X86FaultBase("Debug", "#DB", 1)
212 {}
213 };
214
215 class NonMaskableInterrupt : public X86Interrupt
216 {
217 public:
218 NonMaskableInterrupt(uint8_t _vector) :
219 X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
220 {}
221 };
222
223 class Breakpoint : public X86Trap
224 {
225 public:
226 Breakpoint() :
227 X86Trap("Breakpoint", "#BP", 3)
228 {}
229 };
230
231 class OverflowTrap : public X86Trap
232 {
233 public:
234 OverflowTrap() :
235 X86Trap("Overflow", "#OF", 4)
236 {}
237 };
238
239 class BoundRange : public X86Fault
240 {
241 public:
242 BoundRange() :
243 X86Fault("Bound-Range", "#BR", 5)
244 {}
245 };
246
247 class InvalidOpcode : public X86Fault
248 {
249 public:
250 InvalidOpcode() :
251 X86Fault("Invalid-Opcode", "#UD", 6)
252 {}
253 };
254
255 class DeviceNotAvailable : public X86Fault
256 {
257 public:
258 DeviceNotAvailable() :
259 X86Fault("Device-Not-Available", "#NM", 7)
260 {}
261 };
262
263 class DoubleFault : public X86Abort
264 {
265 public:
266 DoubleFault() :
267 X86Abort("Double-Fault", "#DF", 8, 0)
268 {}
269 };
270
271 class InvalidTSS : public X86Fault
272 {
273 public:
274 InvalidTSS(uint32_t _errorCode) :
275 X86Fault("Invalid-TSS", "#TS", 10, _errorCode)
276 {}
277 };
278
279 class SegmentNotPresent : public X86Fault
280 {
281 public:
282 SegmentNotPresent(uint32_t _errorCode) :
283 X86Fault("Segment-Not-Present", "#NP", 11, _errorCode)
284 {}
285 };
286
287 class StackFault : public X86Fault
288 {
289 public:
290 StackFault(uint32_t _errorCode) :
291 X86Fault("Stack", "#SS", 12, _errorCode)
292 {}
293 };
294
295 class GeneralProtection : public X86Fault
296 {
297 public:
298 GeneralProtection(uint32_t _errorCode) :
299 X86Fault("General-Protection", "#GP", 13, _errorCode)
300 {}
301 };
302
303 class PageFault : public X86Fault
304 {
305 protected:
306 BitUnion32(PageFaultErrorCode)
307 Bitfield<0> present;
308 Bitfield<1> write;
309 Bitfield<2> user;
310 Bitfield<3> reserved;
311 Bitfield<4> fetch;
312 EndBitUnion(PageFaultErrorCode)
313
314 Addr addr;
315
316 public:
317 PageFault(Addr _addr, uint32_t _errorCode) :
318 X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
319 {}
320
321 PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
322 bool user, bool reserved) :
323 X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
324 {
325 PageFaultErrorCode code = 0;
326 code.present = present;
327 code.write = (mode == BaseTLB::Write);
328 code.user = user;
329 code.reserved = reserved;
330 code.fetch = (mode == BaseTLB::Execute);
331 errorCode = code;
332 }
333
|
330 void invoke(ThreadContext * tc);
| 334 void invoke(ThreadContext * tc,
335 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
331
332#if FULL_SYSTEM
333 virtual std::string describe() const;
334#endif
335 };
336
337 class X87FpExceptionPending : public X86Fault
338 {
339 public:
340 X87FpExceptionPending() :
341 X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
342 {}
343 };
344
345 class AlignmentCheck : public X86Fault
346 {
347 public:
348 AlignmentCheck() :
349 X86Fault("Alignment-Check", "#AC", 17, 0)
350 {}
351 };
352
353 class MachineCheck : public X86Abort
354 {
355 public:
356 MachineCheck() :
357 X86Abort("Machine-Check", "#MC", 18)
358 {}
359 };
360
361 class SIMDFloatingPointFault : public X86Fault
362 {
363 public:
364 SIMDFloatingPointFault() :
365 X86Fault("SIMD Floating-Point", "#XF", 19)
366 {}
367 };
368
369 class SecurityException : public X86FaultBase
370 {
371 public:
372 SecurityException() :
373 X86FaultBase("Security Exception", "#SX", 30)
374 {}
375 };
376
377 class ExternalInterrupt : public X86Interrupt
378 {
379 public:
380 ExternalInterrupt(uint8_t _vector) :
381 X86Interrupt("External Interrupt", "#INTR", _vector)
382 {}
383 };
384
385 class SystemManagementInterrupt : public X86Interrupt
386 {
387 public:
388 SystemManagementInterrupt() :
389 X86Interrupt("System Management Interrupt", "#SMI", 0)
390 {}
391 };
392
393 class InitInterrupt : public X86Interrupt
394 {
395 public:
396 InitInterrupt(uint8_t _vector) :
397 X86Interrupt("INIT Interrupt", "#INIT", _vector)
398 {}
399
| 336
337#if FULL_SYSTEM
338 virtual std::string describe() const;
339#endif
340 };
341
342 class X87FpExceptionPending : public X86Fault
343 {
344 public:
345 X87FpExceptionPending() :
346 X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
347 {}
348 };
349
350 class AlignmentCheck : public X86Fault
351 {
352 public:
353 AlignmentCheck() :
354 X86Fault("Alignment-Check", "#AC", 17, 0)
355 {}
356 };
357
358 class MachineCheck : public X86Abort
359 {
360 public:
361 MachineCheck() :
362 X86Abort("Machine-Check", "#MC", 18)
363 {}
364 };
365
366 class SIMDFloatingPointFault : public X86Fault
367 {
368 public:
369 SIMDFloatingPointFault() :
370 X86Fault("SIMD Floating-Point", "#XF", 19)
371 {}
372 };
373
374 class SecurityException : public X86FaultBase
375 {
376 public:
377 SecurityException() :
378 X86FaultBase("Security Exception", "#SX", 30)
379 {}
380 };
381
382 class ExternalInterrupt : public X86Interrupt
383 {
384 public:
385 ExternalInterrupt(uint8_t _vector) :
386 X86Interrupt("External Interrupt", "#INTR", _vector)
387 {}
388 };
389
390 class SystemManagementInterrupt : public X86Interrupt
391 {
392 public:
393 SystemManagementInterrupt() :
394 X86Interrupt("System Management Interrupt", "#SMI", 0)
395 {}
396 };
397
398 class InitInterrupt : public X86Interrupt
399 {
400 public:
401 InitInterrupt(uint8_t _vector) :
402 X86Interrupt("INIT Interrupt", "#INIT", _vector)
403 {}
404
|
400 void invoke(ThreadContext * tc);
| 405 void invoke(ThreadContext * tc,
406 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
401 };
402
403 class StartupInterrupt : public X86Interrupt
404 {
405 public:
406 StartupInterrupt(uint8_t _vector) :
407 X86Interrupt("Startup Interrupt", "#SIPI", _vector)
408 {}
409
| 407 };
408
409 class StartupInterrupt : public X86Interrupt
410 {
411 public:
412 StartupInterrupt(uint8_t _vector) :
413 X86Interrupt("Startup Interrupt", "#SIPI", _vector)
414 {}
415
|
410 void invoke(ThreadContext * tc);
| 416 void invoke(ThreadContext * tc,
417 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
411 };
412
413 class SoftwareInterrupt : public X86Interrupt
414 {
415 public:
416 SoftwareInterrupt(uint8_t _vector) :
417 X86Interrupt("Software Interrupt", "#INTR", _vector)
418 {}
419
420 bool isSoft()
421 {
422 return true;
423 }
424 };
425};
426
427#endif // __ARCH_X86_FAULTS_HH__
| 418 };
419
420 class SoftwareInterrupt : public X86Interrupt
421 {
422 public:
423 SoftwareInterrupt(uint8_t _vector) :
424 X86Interrupt("Software Interrupt", "#INTR", _vector)
425 {}
426
427 bool isSoft()
428 {
429 return true;
430 }
431 };
432};
433
434#endif // __ARCH_X86_FAULTS_HH__
|