tlb.cc (9423:43caa4ca5979) tlb.cc (9738:304a37519d11)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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843
844Fault
845TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
846{
847 panic("Not implemented\n");
848 return NoFault;
849}
850
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 834 unchanged lines hidden (view full) ---

843
844Fault
845TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
846{
847 panic("Not implemented\n");
848 return NoFault;
849}
850
851Fault
852TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
853{
854 return NoFault;
855}
856
851Cycles
852TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
853{
854 Addr va = pkt->getAddr();
855 ASI asi = (ASI)pkt->req->getAsi();
856 uint64_t temp;
857
858 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",

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858TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
859{
860 Addr va = pkt->getAddr();
861 ASI asi = (ASI)pkt->req->getAsi();
862 uint64_t temp;
863
864 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",

--- 565 unchanged lines hidden ---