tlb.cc (8748:01be402c5bf1) tlb.cc (8751:a6c772fef2f1)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/IPR.hh"
42#include "debug/TLB.hh"
43#include "mem/packet_access.hh"
44#include "mem/request.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/IPR.hh"
42#include "debug/TLB.hh"
43#include "mem/packet_access.hh"
44#include "mem/request.hh"
45#include "sim/full_system.hh"
45#include "sim/system.hh"
46
47/* @todo remove some of the magic constants. -- ali
48 * */
49namespace SparcISA {
50
51TLB::TLB(const Params *p)
52 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),

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492 real = true;
493 context = 0;
494 } else {
495 e = lookup(vaddr, part_id, false, context);
496 }
497
498 if (e == NULL || !e->valid) {
499 writeTagAccess(vaddr, context);
46#include "sim/system.hh"
47
48/* @todo remove some of the magic constants. -- ali
49 * */
50namespace SparcISA {
51
52TLB::TLB(const Params *p)
53 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),

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493 real = true;
494 context = 0;
495 } else {
496 e = lookup(vaddr, part_id, false, context);
497 }
498
499 if (e == NULL || !e->valid) {
500 writeTagAccess(vaddr, context);
500 if (real)
501 if (real) {
501 return new InstructionRealTranslationMiss;
502 return new InstructionRealTranslationMiss;
502 else
503#if FULL_SYSTEM
504 return new FastInstructionAccessMMUMiss;
505#else
506 return new FastInstructionAccessMMUMiss(req->getVaddr());
507#endif
503 } else {
504 if (FullSystem)
505 return new FastInstructionAccessMMUMiss;
506 else
507 return new FastInstructionAccessMMUMiss(req->getVaddr());
508 }
508 }
509
510 // were not priviledged accesing priv page
511 if (!priv && e->pte.priv()) {
512 writeTagAccess(vaddr, context);
513 writeSfsr(false, ct, false, PrivViolation, asi);
514 return new InstructionAccessException;
515 }

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704 return NoFault;
705 }
706
707 e = lookup(vaddr, part_id, real, context);
708
709 if (e == NULL || !e->valid) {
710 writeTagAccess(vaddr, context);
711 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
509 }
510
511 // were not priviledged accesing priv page
512 if (!priv && e->pte.priv()) {
513 writeTagAccess(vaddr, context);
514 writeSfsr(false, ct, false, PrivViolation, asi);
515 return new InstructionAccessException;
516 }

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705 return NoFault;
706 }
707
708 e = lookup(vaddr, part_id, real, context);
709
710 if (e == NULL || !e->valid) {
711 writeTagAccess(vaddr, context);
712 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
712 if (real)
713 if (real) {
713 return new DataRealTranslationMiss;
714 return new DataRealTranslationMiss;
714 else
715#if FULL_SYSTEM
716 return new FastDataAccessMMUMiss;
717#else
718 return new FastDataAccessMMUMiss(req->getVaddr());
719#endif
715 } else {
716 if (FullSystem)
717 return new FastDataAccessMMUMiss;
718 else
719 return new FastDataAccessMMUMiss(req->getVaddr());
720 }
720
721 }
722
723 if (!priv && e->pte.priv()) {
724 writeTagAccess(vaddr, context);
725 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
726 return new DataAccessException;
727 }

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722 }
723
724 if (!priv && e->pte.priv()) {
725 writeTagAccess(vaddr, context);
726 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
727 return new DataAccessException;
728 }

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