tlb.cc (7811:a8fc35183c10) | tlb.cc (8105:906864dd0937) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 802 unchanged lines hidden (view full) --- 811 return new PrivilegedAction; 812 } 813 goto regAccessOk; 814 815 816regAccessOk: 817handleMmuRegAccess: 818 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 802 unchanged lines hidden (view full) --- 811 return new PrivilegedAction; 812 } 813 goto regAccessOk; 814 815 816regAccessOk: 817handleMmuRegAccess: 818 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); |
819 req->setFlags(Request::MMAPED_IPR); | 819 req->setFlags(Request::MMAPPED_IPR); |
820 req->setPaddr(req->getVaddr()); 821 return NoFault; 822}; 823 824Fault 825TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 826{ 827 if (mode == Execute) --- 590 unchanged lines hidden --- | 820 req->setPaddr(req->getVaddr()); 821 return NoFault; 822}; 823 824Fault 825TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 826{ 827 if (mode == Execute) --- 590 unchanged lines hidden --- |